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Bump to scala 2.13/chisel 3.5.5/latest rocketchip #74

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Feb 1, 2023
Merged

Bump to scala 2.13/chisel 3.5.5/latest rocketchip #74

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0ea2722
Bump to scala 2.13/chisel 3.5.5/latest rocketchip
jerryz123 Jan 4, 2023
956e2fb
Use SLLI/SRAI/SRLI_RV32 variants
jerryz123 Jan 12, 2023
9265d02
Bump to latest rocket-chip
jerryz123 Jan 18, 2023
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2 changes: 1 addition & 1 deletion build.sbt
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Expand Up @@ -6,5 +6,5 @@ version := "2.0"

name := "sodor"

scalaVersion := "2.12.10"
scalaVersion := "2.13.10"

2 changes: 1 addition & 1 deletion scripts/instructions.py
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Expand Up @@ -911,7 +911,7 @@ def __getitem__(self, i):
LD_OPCODES = {LB, LH, LW, LD, LBU, LHU, LWU}
ST_OPCODES = {SB, SH, SW, SD}
LDST_OPCODES = LD_OPCODES | ST_OPCODES
ARITH_OPCODES = {LUI, AUIPC, ADDI, SLLI, SLTI, SLTIU, XORI, SRLI, SRAI, ORI, ANDI,
ARITH_OPCODES = {LUI, AUIPC, ADDI, SLLI_RV32, SLTI, SLTIU, XORI, SRLI_RV32, SRAI_RV32, ORI, ANDI,
ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
ADDIW, SLLIW, SRLIW, SRAIW,
ADDW, SUBW, SLLW, SRLW, SRAW,
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6 changes: 3 additions & 3 deletions src/main/scala/common/instructions.scala
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Expand Up @@ -19,12 +19,12 @@ object Instructions {
def LUI = BitPat("b?????????????????????????0110111")
def AUIPC = BitPat("b?????????????????????????0010111")
def ADDI = BitPat("b?????????????????000?????0010011")
def SLLI = BitPat("b000000???????????001?????0010011")
//def SLLI = BitPat("b000000???????????001?????0010011")
def SLTI = BitPat("b?????????????????010?????0010011")
def SLTIU = BitPat("b?????????????????011?????0010011")
def XORI = BitPat("b?????????????????100?????0010011")
def SRLI = BitPat("b000000???????????101?????0010011")
def SRAI = BitPat("b010000???????????101?????0010011")
//def SRLI = BitPat("b000000???????????101?????0010011")
//def SRAI = BitPat("b010000???????????101?????0010011")
def ORI = BitPat("b?????????????????110?????0010011")
def ANDI = BitPat("b?????????????????111?????0010011")
def ADD = BitPat("b0000000??????????000?????0110011")
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5 changes: 5 additions & 0 deletions src/main/scala/common/sodor_tile.scala
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Expand Up @@ -61,6 +61,11 @@ case class SodorCoreParams(
val fetchWidth: Int = 1 // TODO: Check
val retireWidth: Int = 1
val nPTECacheEntries: Int = 0
val useBitManip: Boolean = false
val useBitManipCrypto: Boolean = false
val useCryptoNIST: Boolean = false
val useCryptoSM: Boolean = false
val traceHasWdata: Boolean = false
}

// DOC include start: CanAttachTile
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6 changes: 3 additions & 3 deletions src/main/scala/rv32_1stage/cpath.scala
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Expand Up @@ -69,9 +69,9 @@ class CtlPath(implicit val conf: SodorCoreParams) extends Module
XORI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLTI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLTIU -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLTU, WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLLI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRAI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRLI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLLI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRAI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRLI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),

SLL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
ADD -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_1stage/dpath.scala
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Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket.{CSRFile, Causes}
import freechips.rocketchip.tile.CoreInterrupts

import Constants._
import sodor.stage1.Constants._
import sodor.common._

class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()
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8 changes: 4 additions & 4 deletions src/main/scala/rv32_2stage/cpath.scala
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Expand Up @@ -13,7 +13,7 @@ import freechips.rocketchip.rocket.{CSR, Causes}

import sodor.common._
import sodor.common.Instructions._
import Constants._
import sodor.stage2.Constants._

class CtlToDatIo extends Bundle()
{
Expand Down Expand Up @@ -72,9 +72,9 @@ class CtlPath(implicit val conf: SodorCoreParams) extends Module
XORI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLTI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLTIU -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLTU, WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLLI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRAI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRLI -> List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SLLI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRAI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
SRLI_RV32->List(Y, BR_N , OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),

SLL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
ADD -> List(Y, BR_N , OP1_RS1, OP2_RS2 , ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N),
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_2stage/dpath.scala
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Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket.{CSRFile, Causes}
import freechips.rocketchip.tile.CoreInterrupts

import Constants._
import sodor.stage2.Constants._
import sodor.common._

class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_3stage/alu.scala
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Expand Up @@ -8,7 +8,7 @@ import chisel3._
import chisel3.util._

import sodor.common._
import Constants._
import sodor.stage3.Constants._

object ALU
{
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10 changes: 5 additions & 5 deletions src/main/scala/rv32_3stage/cpath.scala
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Expand Up @@ -14,8 +14,8 @@ import freechips.rocketchip.rocket.{CSR, Causes}

import sodor.common._
import sodor.common.Instructions._
import Constants._
import ALU._
import sodor.stage3.Constants._
import sodor.stage3.ALU._

class CtrlSignals extends Bundle()
{
Expand Down Expand Up @@ -80,9 +80,9 @@ class CtlPath(implicit val conf: SodorCoreParams) extends Module
XORI -> List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_XOR , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SLTI -> List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SLT , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SLTIU -> List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SLTU, WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SLLI -> List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SRAI -> List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SRLI -> List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SLLI_RV32->List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SLL , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SRAI_RV32->List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SRA , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
SRLI_RV32->List(Y, BR_N , N, OP1_RS1, OP2_IMI , ALU_SRL , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),

SLL -> List(Y, BR_N , N, OP1_RS1, OP2_RS2 , ALU_SLL , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
ADD -> List(Y, BR_N , N, OP1_RS1, OP2_RS2 , ALU_ADD , WB_ALU, REN_1, Y, MEN_0, M_X , MT_X, CSR.N, M_N),
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_3stage/dpath.scala
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Expand Up @@ -21,7 +21,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket.{CSR, CSRFile, Causes}
import freechips.rocketchip.tile.CoreInterrupts

import Constants._
import sodor.stage3.Constants._
import sodor.common._

class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_3stage/frontend.scala
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Expand Up @@ -30,7 +30,7 @@ import chisel3._
import chisel3.util._


import Constants._
import sodor.stage3.Constants._
import sodor.common._


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8 changes: 4 additions & 4 deletions src/main/scala/rv32_5stage/cpath.scala
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Expand Up @@ -15,7 +15,7 @@ import chisel3.util._

import freechips.rocketchip.rocket.{CSR, Causes}

import Constants._
import sodor.stage5.Constants._
import sodor.common._
import sodor.common.Instructions._

Expand Down Expand Up @@ -83,9 +83,9 @@ class CtlPath(implicit val conf: SodorCoreParams) extends Module
XORI -> List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SLTI -> List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SLTIU -> List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SLTU, WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SLLI -> List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SRAI -> List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SRLI -> List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SLLI_RV32->List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SRAI_RV32->List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
SRLI_RV32->List(Y, BR_N , OP1_RS1, OP2_ITYPE , OEN_1, OEN_0, ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),

SLL -> List(Y, BR_N , OP1_RS1, OP2_RS2 , OEN_1, OEN_1, ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
ADD -> List(Y, BR_N , OP1_RS1, OP2_RS2 , OEN_1, OEN_1, ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, CSR.N, N),
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_5stage/dpath.scala
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Expand Up @@ -16,7 +16,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket.{CSR, CSRFile, Causes}
import freechips.rocketchip.tile.CoreInterrupts

import Constants._
import sodor.stage5.Constants._
import sodor.common._

class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_5stage/regfile.scala
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Expand Up @@ -9,7 +9,7 @@ import chisel3._
import chisel3.util._


import Constants._
import sodor.stage5.Constants._
import sodor.common._

class RFileIo(implicit val conf: SodorCoreParams) extends Bundle()
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_ucode/cpath.scala
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Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.rocket.CSR

import sodor.common._
import sodor.common.Instructions._
import Constants._
import sodor.ucode.Constants._
import scala.collection.mutable.ArrayBuffer


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2 changes: 1 addition & 1 deletion src/main/scala/rv32_ucode/dpath.scala
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Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.rocket.CSRFile
import freechips.rocketchip.tile.CoreInterrupts

import Constants._
import sodor.ucode.Constants._
import sodor.common._

class DatToCtlIo extends Bundle()
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2 changes: 1 addition & 1 deletion src/main/scala/rv32_ucode/microcode.scala
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Expand Up @@ -49,7 +49,7 @@ import chisel3.util._

import freechips.rocketchip.rocket.CSR

import Constants._
import sodor.ucode.Constants._
import sodor.common._

object Microcode
Expand Down