Bump to scala 2.13/chisel 3.5.5/latest rocketchip

ucb-bar · Jan 11, 2023 · 0ea2722 · 0ea2722
1 parent 1ed40b3
commit 0ea2722
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Showing 14 changed files with 15 additions and 15 deletions.
diff --git a/build.sbt b/build.sbt
@@ -6,5 +6,5 @@ version := "2.0"
 
 name := "sodor"
 
-scalaVersion := "2.12.10"
+scalaVersion := "2.13.10"
 
diff --git a/src/main/scala/rv32_1stage/dpath.scala b/src/main/scala/rv32_1stage/dpath.scala
@@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.{CSRFile, Causes}
 import freechips.rocketchip.tile.CoreInterrupts
 
-import Constants._
+import sodor.stage1.Constants._
 import sodor.common._
 
 class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()

diff --git a/src/main/scala/rv32_2stage/cpath.scala b/src/main/scala/rv32_2stage/cpath.scala
@@ -13,7 +13,7 @@ import freechips.rocketchip.rocket.{CSR, Causes}
 
 import sodor.common._
 import sodor.common.Instructions._
-import Constants._
+import sodor.stage2.Constants._
 
 class CtlToDatIo extends Bundle()
 {

diff --git a/src/main/scala/rv32_2stage/dpath.scala b/src/main/scala/rv32_2stage/dpath.scala
@@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.{CSRFile, Causes}
 import freechips.rocketchip.tile.CoreInterrupts
 
-import Constants._
+import sodor.stage2.Constants._
 import sodor.common._
 
 class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()

diff --git a/src/main/scala/rv32_3stage/alu.scala b/src/main/scala/rv32_3stage/alu.scala
@@ -8,7 +8,7 @@ import chisel3._
 import chisel3.util._
 
 import sodor.common._
-import Constants._
+import sodor.stage3.Constants._
 
 object ALU
 {

diff --git a/src/main/scala/rv32_3stage/cpath.scala b/src/main/scala/rv32_3stage/cpath.scala
@@ -14,8 +14,8 @@ import freechips.rocketchip.rocket.{CSR, Causes}
 
 import sodor.common._
 import sodor.common.Instructions._
-import Constants._
-import ALU._
+import sodor.stage3.Constants._
+import sodor.stage3.ALU._
 
 class CtrlSignals extends Bundle()
 {

diff --git a/src/main/scala/rv32_3stage/dpath.scala b/src/main/scala/rv32_3stage/dpath.scala
@@ -21,7 +21,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.{CSR, CSRFile, Causes}
 import freechips.rocketchip.tile.CoreInterrupts
 
-import Constants._
+import sodor.stage3.Constants._
 import sodor.common._
 
 class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()

diff --git a/src/main/scala/rv32_3stage/frontend.scala b/src/main/scala/rv32_3stage/frontend.scala
@@ -30,7 +30,7 @@ import chisel3._
 import chisel3.util._
 
 
-import Constants._
+import sodor.stage3.Constants._
 import sodor.common._
 
 

diff --git a/src/main/scala/rv32_5stage/cpath.scala b/src/main/scala/rv32_5stage/cpath.scala
@@ -15,7 +15,7 @@ import chisel3.util._
 
 import freechips.rocketchip.rocket.{CSR, Causes}
 
-import Constants._
+import sodor.stage5.Constants._
 import sodor.common._
 import sodor.common.Instructions._
 

diff --git a/src/main/scala/rv32_5stage/dpath.scala b/src/main/scala/rv32_5stage/dpath.scala
@@ -16,7 +16,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.{CSR, CSRFile, Causes}
 import freechips.rocketchip.tile.CoreInterrupts
 
-import Constants._
+import sodor.stage5.Constants._
 import sodor.common._
 
 class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()

diff --git a/src/main/scala/rv32_5stage/regfile.scala b/src/main/scala/rv32_5stage/regfile.scala
@@ -9,7 +9,7 @@ import chisel3._
 import chisel3.util._
 
 
-import Constants._
+import sodor.stage5.Constants._
 import sodor.common._
 
 class RFileIo(implicit val conf: SodorCoreParams) extends Bundle()

diff --git a/src/main/scala/rv32_ucode/cpath.scala b/src/main/scala/rv32_ucode/cpath.scala
@@ -14,7 +14,7 @@ import freechips.rocketchip.rocket.CSR
 
 import sodor.common._
 import sodor.common.Instructions._
-import Constants._
+import sodor.ucode.Constants._
 import scala.collection.mutable.ArrayBuffer
 
 

diff --git a/src/main/scala/rv32_ucode/dpath.scala b/src/main/scala/rv32_ucode/dpath.scala
@@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.CSRFile
 import freechips.rocketchip.tile.CoreInterrupts
 
-import Constants._
+import sodor.ucode.Constants._
 import sodor.common._
 
 class DatToCtlIo extends Bundle()

diff --git a/src/main/scala/rv32_ucode/microcode.scala b/src/main/scala/rv32_ucode/microcode.scala
@@ -49,7 +49,7 @@ import chisel3.util._
 
 import freechips.rocketchip.rocket.CSR
 
-import Constants._
+import sodor.ucode.Constants._
 import sodor.common._
 
 object Microcode
Original file line number	Diff line number	Diff line change
Expand Up		@@ -6,5 +6,5 @@ version := "2.0"

		name := "sodor"

		scalaVersion := "2.12.10"
		scalaVersion := "2.13.10"