patch in fix

ucb-bar · Nov 20, 2024 · 2b1aa53 · 2b1aa53
1 parent 530454d
commit 2b1aa53
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/src/main/scala/gemmini/Scratchpad.scala b/src/main/scala/gemmini/Scratchpad.scala
@@ -498,9 +498,15 @@ class Scratchpad[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T,
 
         bio.read.resp.ready := Mux(bio.read.resp.bits.fromDMA, dma_read_resp.ready, ex_read_resp.ready)
 
+        /*
         dma_read_pipe.ready := writer.module.io.req.ready &&
           !write_issue_q.io.deq.bits.laddr.is_acc_addr && write_issue_q.io.deq.bits.laddr.sp_bank() === i.U && // I believe we don't need to check that write_issue_q is valid here, because if the SRAM's resp is valid, then that means that the write_issue_q's deq should also be valid
           !write_issue_q.io.deq.bits.laddr.is_garbage()
+          */
+        dma_read_pipe.ready := writer.module.io.req.ready &&
+          ((!write_issue_q.io.deq.bits.laddr.is_acc_addr && write_issue_q.io.deq.bits.laddr.sp_bank() === i.U) && write_issue_q.io.deq.valid) &&
+          !write_issue_q.io.deq.bits.laddr.is_garbage()
+
         when (dma_read_pipe.fire) {
           writeData.valid := true.B
           writeData.bits := dma_read_pipe.bits.data