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Add Chip ID Pin and Port #1721
Add Chip ID Pin and Port #1721
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generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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Let's just fix up some naming, then we can merge this.
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It looks like a lot of the configs don't like this pin, so we should disable it in AbstractConfig.
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Adds a chip ID port that is used to assign a chip ID to each chip within a config. The port drives a MMIO register (see testchipip/#212). Currently, the port value is hardcoded in WithChipIdPinFromHarness, but the harness binder will be modified in the future to use the chipId argument (see #1716).
The purpose of this PR is to enable cache coherency across multi-chip configs in Chipyard.
Related PRs / Issues:
Type of change:
Impact:
Contributor Checklist:
main
as the base branch?changelog:<topic>
label?changelog:
label?.conda-lock.yml
file if you updated the conda requirements file?Please Backport
?