Add PortAPI between IO and Harness blocks #1610
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jerryz123
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| @@ -55,6 +55,16 @@ class WithScalaTestFeatures extends Config((site, here, up) => { | |||
| case TracePortKey => up(TracePortKey, site).map(_.copy(print = true)) | |||
| }) | |||
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| // Multi-cycle regfile for rocket+boom | |||
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Out of scope of this PR? If this PR takes a while to merge we can separate it out.
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This fixes the old IOBInder-based approach for adding these annotations, to a simpler match statement at the FireSim top level.
| case class ExtIntPort (val io: UInt) | ||
| extends Port[UInt] | ||
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| case class DMIPort (val io: ClockedDMIIO) |
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How do you deal with Parameters in these case classes? Sometimes the IO depends on p: Parameters?
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Answered offline. The IO is constructed outside of this case class, thus you don't need the parameters to generate the IO.
| case class I2CPort (val io: sifive.blocks.devices.i2c.I2CPort) | ||
| extends Port[sifive.blocks.devices.i2c.I2CPort] |
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Nit: Why is this fully qualified?
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Because sifive.I2CPort name conflicts with this I2CPort. Ugly, unfortunately
| // TODO FIX: This currently makes each SimDRAM contain the entire memory space | ||
| val memSize = port.params.master.size | ||
| val memBase = port.params.master.base | ||
| val lineSize = 64 // cache block size |
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LineSize isn't parameterized anymore?
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line_size doesn't actually matter for DRAM. We shouldn't even be passing it back to DRAMSim in the first place (and our DRAMSim driver doesn't use the line_size parameter for any calculations). It also requires line_size=64.
Future TODO is to remove the line_size argument to DRAMSim, so we can get rid of this here as well too.
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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This adds
trait iobinders.Port, which represents some IO bundle that should be exposed by ChipTop, and connected to in the Harness. Case classes extending this trait should package enough parameter information about the IO bundle to facilitate harness instantiation and/or IO-cell generation.Changes:
Portobjects, instead of raw IO. ThePortobject contains the IO, as well as parameterization information around the IOPorts emitted by the ChipTop. This is only a cosmetic change to the implementationsPorts to connect.Unfortunately, due to the API change, the surface area of this PR is quite large. The main places to look are in
chipyard/src/main/scala/iobinders/Ports.scala, to see the case classes describing top-level ports, as well aschipyard/src/main/scala/harness/HarnessBinders.scala, to see the updated HarnessBinder APIRelated PRs / Issues:
Type of change:
Impact:
Contributor Checklist:
mainas the base branch?changelog:<topic>label?changelog:label?.conda-lock.ymlfile if you updated the conda requirements file?Please Backport?