ucb-bar · jerryz123 · Apr 8, 2023 · Mar 21, 2023 · Mar 29, 2023 · Mar 29, 2023
diff --git a/.gitmodules b/.gitmodules
@@ -73,9 +73,6 @@
 [submodule "fpga/fpga-shells"]
 	path = fpga/fpga-shells
 	url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
-[submodule "tools/api-config-chipsalliance"]
-	path = tools/api-config-chipsalliance
-	url = https://github.com/chipsalliance/api-config-chipsalliance.git
 [submodule "tools/rocket-dsp-utils"]
 	path = tools/rocket-dsp-utils
 	url = https://github.com/ucb-bar/rocket-dsp-utils
@@ -121,3 +118,6 @@
 [submodule "generators/mempress"]
 	path = generators/mempress
 	url = https://github.com/ucb-bar/mempress.git
+[submodule "tools/cde"]
+	path = tools/cde
+	url = https://github.com/chipsalliance/cde.git
diff --git a/build.sbt b/build.sbt
@@ -62,7 +62,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
   new Group(test.name, Seq(test), SubProcess(options))
 } toSeq
 
-val chiselVersion = "3.5.5"
+val chiselVersion = "3.5.6"
 
 lazy val chiselSettings = Seq(
   libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
@@ -102,18 +102,8 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
     )
   )
 
-lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
-  .settings(commonSettings)
-  .settings(
-    libraryDependencies ++= Seq(
-      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
-      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
-    )
-  )
-
 lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-  .dependsOn(hardfloat, rocketMacros, rocketConfig)
+  .dependsOn(hardfloat, rocketMacros, cde)
   .settings(commonSettings)
   .settings(chiselSettings)
   .settings(
@@ -246,16 +236,12 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
       "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
   ))
 
-lazy val `api-config-chipsalliance` = freshProject("api-config-chipsalliance", file("./tools/api-config-chipsalliance"))
-  .settings(
-    commonSettings,
-    libraryDependencies ++= Seq(
-      "org.scalatest" %% "scalatest" % "3.0.+" % "test",
-      "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
-    ))
+lazy val cde = (project in file("tools/cde"))
+  .settings(commonSettings)
+  .settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip")
 
 lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils"))
-  .dependsOn(rocketchip, `api-config-chipsalliance`, dsptools)
+  .dependsOn(rocketchip, cde, dsptools)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 

diff --git a/fpga/fpga-shells b/fpga/fpga-shells
diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 package chipyard.fpga.arty
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
@@ -17,9 +17,9 @@ import chipyard.{BuildSystem}
 
 // DOC include start: AbstractArty and Rocket
 class WithArtyTweaks extends Config(
+  new WithArtyResetHarnessBinder ++
   new WithArtyJTAGHarnessBinder ++
   new WithArtyUARTHarnessBinder ++
-  new WithArtyResetHarnessBinder ++
   new WithDebugResetPassthrough ++
 
   new chipyard.config.WithDTSTimebase(32768) ++

diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.arty
 
 import chisel3._
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 import freechips.rocketchip.jtag.{JTAGIO}
 
 import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
@@ -15,15 +15,15 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
 import chipyard.iobinders.JTAGChipIO
 
 class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
-  (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
-    require(ports.size == 2)
-
+  (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
+    val resetPorts = ports.collect { case b: Bool => b }
+    require(resetPorts.size == 2)
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       // Debug module reset
-      th.dut_ndreset := ports(0)
+      th.dut_ndreset := resetPorts(0)
 
       // JTAG reset
-      ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
+      resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
     }
   }
 })
@@ -63,6 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
         io_jtag.TMS.i.po.map(_ := DontCare)
         io_jtag.TDO.i.po.map(_ := DontCare)
       }
+      case b: Bool =>
     }
   }
 })

diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala
@@ -3,12 +3,12 @@ package chipyard.fpga.arty
 import chisel3._
 import chisel3.experimental.{IO}
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 
 import chipyard.iobinders.{ComposeIOBinder}
 
 class WithDebugResetPassthrough extends ComposeIOBinder({
-  (system: HasPeripheryDebugModuleImp) => {
+  (system: HasPeripheryDebug) => {
     // Debug module reset
     val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
     io_ndreset := system.debug.get.ndreset

diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.arty
 import chisel3._
 
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
 

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 package chipyard.fpga.arty100t
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._

diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.arty100t
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
 
 import sifive.fpgashells.shell.xilinx._

diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -2,7 +2,6 @@ package chipyard.fpga.arty100t
 
 import chisel3._
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}

diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vc707
 
 import sys.process._
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
 import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}

diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
 
 import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}

diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118
 
 import sys.process._
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
 import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}

diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118
 import chisel3._
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
 
 import sifive.fpgashells.shell._

diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
 
 import sifive.fpgashells.shell.xilinx._

diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup
 
 import math.min
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.diplomacy._

diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{attach}
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
 
 import sifive.fpgashells.shell._

diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._

diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118.bringup
 import chisel3._
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 

diff --git a/generators/boom b/generators/boom
diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -6,7 +6,7 @@ import scala.collection.mutable.{ArrayBuffer}
 
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import chipyard.iobinders._

diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IntParam, StringParam, IO}
 import chisel3.util._
 
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.devices.tilelink._

diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 
 // ------------------------------------

diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
 
-import freechips.rocketchip.config.{Field, Config, Parameters}
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
 import freechips.rocketchip.devices.debug._

diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -3,7 +3,7 @@ package chipyard.iobinders
 import chisel3._
 import chisel3.experimental.{Analog, IO, DataMirror}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.jtag.{JTAGIO}
@@ -219,7 +219,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
     def clockBundle = clockSinkNode.get.in.head._1
 
 
-    InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => {
+    InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => {
       system.debug.map({ debug =>
         // We never use the PSDIO, so tie it off on-chip
         system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }

diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{IntParam, StringParam, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._

diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -9,9 +9,9 @@ import chisel3._
 import chisel3.internal.sourceinfo.{SourceInfo}
 
 import freechips.rocketchip.prci._
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, ExportDebug, DebugModuleKey}
 import sifive.blocks.devices.uart.{HasPeripheryUART, PeripheryUARTKey}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
@@ -71,6 +71,7 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
 
 class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
   with HasTiles
+  with HasPeripheryDebug
   with CanHaveHTIF
   with CanHaveChosenInDTS
 {

diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
@@ -7,7 +7,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._

diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
 

diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -4,7 +4,7 @@ import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{XLen, TileParams}
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 /**

diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._

diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters, Config, Field}
+import org.chipsalliance.cde.config.{Parameters, Config, Field}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 

diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util.ElaborationArtefacts
+1 −1		src/main/scala/clocks/ClockGroup.scala
+1 −1		src/main/scala/clocks/Nodes.scala
+1 −1		src/main/scala/clocks/PLLFactory.scala
+1 −1		src/main/scala/clocks/Parameters.scala
+1 −1		src/main/scala/clocks/ResetWrangler.scala
+1 −1		src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireDDR3.scala
+1 −1		src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireDDR3Periphery.scala
+1 −1		src/main/scala/devices/microsemi/polarfire_ddr4/MicrosemiPolarFireDDR4.scala
+1 −1		src/main/scala/devices/microsemi/polarfire_ddr4/MicrosemiPolarFireDDR4Periphery.scala
+1 −1		src/main/scala/devices/microsemi/polarfire_pcie/PolarFireEvalKitPCIeX4.scala
+138 −0		src/main/scala/devices/xilinx/allinxaxku040mig/AlinxAxku040MIG.scala
+1 −1		src/main/scala/devices/xilinx/ethernet/ethernet.scala
+1 −1		src/main/scala/devices/xilinx/xdma/XDMA.scala
+1 −1		src/main/scala/devices/xilinx/xilinxarty100tmig/XilinxArty100TMIG.scala
+1 −1		src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
+1 −1		src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+1 −1		src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+1 −1		src/main/scala/devices/xilinx/xilinxvcu118mig/XilinxVCU118MIG.scala
+1 −1		src/main/scala/devices/xilinx/xilinxvcu118mig/XilinxVCU118MIGPeriphery.scala
+1 −1		src/main/scala/ip/microsemi/corejtagdebug/corejtagdebug.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_ccc/PolarFireCCC.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_clock_divider/PolarFireClockDivider.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_ddr3/PolarFireDDR3.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_ddr4/PolarFireDDR4.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_dll/PolarFireDLL.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_glitchless_mux/PolarFireGlitchlessMux.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_init_monitor/PolarFireInitMonitor.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_oscillator/PolarFireOscillator.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_pcie_rootport/PolarFirePCIeRootPort.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_reset/PolarFireReset.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_tx_pll/PolarFireTxPLL.scala
+1 −1		src/main/scala/ip/microsemi/polarfire_xcvr_refclk/PolarFireTransceiverRefClk.scala
+99 −0		src/main/scala/ip/xilinx/alinx_axku040mig/axku040mig.scala
+1 −1		src/main/scala/ip/xilinx/arty100tmig/arty100tmig.scala
+1 −1		src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+1 −1		src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+1 −1		src/main/scala/ip/xilinx/vcu118mig/vcu118mig.scala
+1 −1		src/main/scala/ip/xilinx/xdma/xdma.scala
+1 −1		src/main/scala/ip/xilinx/xxv_ethernet/nfmac10g.scala
+1 −1		src/main/scala/ip/xilinx/xxv_ethernet/xxv_ethernet.scala
+1 −1		src/main/scala/shell/ButtonOverlay.scala
+1 −1		src/main/scala/shell/CTSResetOverlay.scala
+1 −1		src/main/scala/shell/ChipLinkOverlay.scala
+1 −1		src/main/scala/shell/ClockOverlay.scala
+1 −1		src/main/scala/shell/DDROverlay.scala
+1 −1		src/main/scala/shell/Ethernet.scala
+1 −1		src/main/scala/shell/GPIOOverlay.scala
+1 −1		src/main/scala/shell/GPIOPMODOverlay.scala
+1 −1		src/main/scala/shell/I2COverlay.scala
+1 −1		src/main/scala/shell/IOShell.scala
+1 −1		src/main/scala/shell/JTAGDebugBScanOverlay.scala
+1 −1		src/main/scala/shell/JTAGDebugOverlay.scala
+1 −1		src/main/scala/shell/LEDOverlay.scala
+1 −1		src/main/scala/shell/PCIeOverlay.scala
+1 −1		src/main/scala/shell/PMODOverlay.scala
+1 −1		src/main/scala/shell/PWMOverlay.scala
+1 −1		src/main/scala/shell/PinOverlay.scala
+1 −1		src/main/scala/shell/PorGenOverlay.scala
+1 −1		src/main/scala/shell/SPIFlashOverlay.scala
+1 −1		src/main/scala/shell/SPIOverlay.scala
+1 −1		src/main/scala/shell/Shell.scala
+1 −1		src/main/scala/shell/SwitchOverlay.scala
+1 −1		src/main/scala/shell/TracePMODOverlay.scala
+1 −1		src/main/scala/shell/UARTOverlay.scala
+1 −1		src/main/scala/shell/Util.scala
+1 −1		src/main/scala/shell/cJTAGDebugOverlay.scala
+2 −2		src/main/scala/shell/microsemi/PolarFireEvalKitShell.scala
+1 −1		src/main/scala/shell/microsemi/PolarFireShell.scala
+1 −1		src/main/scala/shell/microsemi/VeraShell.scala
+347 −0		src/main/scala/shell/xilinx/AlinxAxku040Shell.scala
+1 −1		src/main/scala/shell/xilinx/Arty100TShell.scala
+2 −2		src/main/scala/shell/xilinx/ArtyShell.scala
+1 −1		src/main/scala/shell/xilinx/PeripheralsVC707Shell.scala
+1 −1		src/main/scala/shell/xilinx/PeripheralsVCU118Shell.scala
+1 −1		src/main/scala/shell/xilinx/UltraScaleShell.scala
+1 −1		src/main/scala/shell/xilinx/VC707NewShell.scala
+2 −2		src/main/scala/shell/xilinx/VC707Shell.scala
+1 −1		src/main/scala/shell/xilinx/VCU118NewShell.scala
+2 −2		src/main/scala/shell/xilinx/VCU118Shell.scala
+1 −1		src/main/scala/shell/xilinx/XilinxShell.scala
+4 −0		xilinx/alinx_axku040/constraints/alinx_axku040.xdc
+3 −0		xilinx/alinx_axku040/tcl/board.tcl
+1 −1		src/main/scala/common/config-mixins.scala
+1 −1		src/main/scala/common/consts.scala
+1 −1		src/main/scala/common/micro-op.scala
+1 −1		src/main/scala/common/parameters.scala
+1 −1		src/main/scala/common/tile.scala
+1 −1		src/main/scala/common/types.scala
+1 −1		src/main/scala/exu/core.scala
+1 −1		src/main/scala/exu/decode.scala
+1 −1		src/main/scala/exu/dispatch.scala
+1 −1		src/main/scala/exu/execution-units/execution-unit.scala
+1 −1		src/main/scala/exu/execution-units/execution-units.scala
+1 −1		src/main/scala/exu/execution-units/fdiv.scala
+1 −1		src/main/scala/exu/execution-units/fpu.scala
+1 −1		src/main/scala/exu/execution-units/functional-unit.scala
+1 −1		src/main/scala/exu/execution-units/rocc.scala
+1 −1		src/main/scala/exu/fp-pipeline.scala
+1 −1		src/main/scala/exu/issue-units/issue-slot.scala
+1 −1		src/main/scala/exu/issue-units/issue-unit-age-ordered.scala
+1 −1		src/main/scala/exu/issue-units/issue-unit-unordered.scala
+1 −1		src/main/scala/exu/issue-units/issue-unit.scala
+1 −1		src/main/scala/exu/register-read/func-unit-decode.scala
+1 −1		src/main/scala/exu/register-read/regfile.scala
+1 −1		src/main/scala/exu/register-read/register-read.scala
+1 −1		src/main/scala/exu/rename/rename-busytable.scala
+1 −1		src/main/scala/exu/rename/rename-freelist.scala
+1 −1		src/main/scala/exu/rename/rename-maptable.scala
+1 −1		src/main/scala/exu/rename/rename-stage.scala
+1 −1		src/main/scala/exu/rob.scala
+1 −1		src/main/scala/ifu/bpd/bim.scala
+1 −1		src/main/scala/ifu/bpd/btb.scala
+1 −1		src/main/scala/ifu/bpd/composer.scala
+1 −1		src/main/scala/ifu/bpd/faubtb.scala
+1 −1		src/main/scala/ifu/bpd/hbim.scala
+1 −1		src/main/scala/ifu/bpd/local.scala
+1 −1		src/main/scala/ifu/bpd/loop.scala
+1 −1		src/main/scala/ifu/bpd/predictor.scala
+1 −1		src/main/scala/ifu/bpd/ras.scala
+1 −1		src/main/scala/ifu/bpd/sw_predictor.scala
+1 −1		src/main/scala/ifu/bpd/tage.scala
+1 −1		src/main/scala/ifu/bpd/tourney.scala
+1 −1		src/main/scala/ifu/bpd/ubtb.scala
+1 −1		src/main/scala/ifu/fetch-buffer.scala
+1 −1		src/main/scala/ifu/fetch-target-queue.scala
+1 −1		src/main/scala/ifu/frontend.scala
+1 −1		src/main/scala/ifu/icache.scala
+1 −1		src/main/scala/lsu/dcache.scala
+1 −1		src/main/scala/lsu/lsu.scala
+1 −1		src/main/scala/lsu/mshrs.scala
+1 −1		src/main/scala/lsu/prefetcher.scala
+1 −1		src/main/scala/lsu/tlb.scala
+1 −1		src/main/scala/lsu/tracegen.scala
+2 −2		src/main/scala/util/util.scala
+1 −1		src/test/scala/RegFileTest.scala
+1 −1		src/test/scala/TestUtils.scala