Merge pull request #1891 from ucb-bar/name_domains

Name all the generated ClockDomains
ucb-bar · May 30, 2024 · eb6910a · eb6910a
2 parents 77972c8 + 2d2abed
commit eb6910a
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diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -37,7 +37,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
 
   // Set up clock domain
   private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
-  val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
+  val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
+    .suggestName("chipyard_prcictrl_domain")
 
   val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
   prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar

diff --git a/generators/rocket-chip b/generators/rocket-chip
diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks
diff --git a/generators/testchipip b/generators/testchipip
+1 −1		src/main/scala/devices/tilelink/BootROM.scala
+1 −1		src/main/scala/devices/tilelink/CLINT.scala
+1 −1		src/main/scala/devices/tilelink/Plic.scala
+2 −0		src/main/scala/prci/ClockDomain.scala
+3 −2		src/main/scala/tilelink/BusWrapper.scala
+4 −0		src/main/resources/testchipip/csrc/cospike_impl.cc
+1 −1		src/main/scala/serdes/PeripheryTLSerial.scala
+14 −8		src/main/scala/serdes/Serdes.scala
+7 −0		src/main/scala/serdes/SerialPhy.scala
+2 −2		src/main/scala/soc/Configs.scala
+1 −0		src/main/scala/soc/Scratchpad.scala