Disable verilator builds of Ara

ucb-bar · Aug 8, 2024 · c1a79f5 · c1a79f5
1 parent ddebdc6
commit c1a79f5
Show file tree

Hide file tree

Showing 4 changed files with 7 additions and 28 deletions.
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
@@ -75,7 +75,7 @@ mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
 mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig"
 mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig"
 mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig"
-mapping["chipyard-shuttleara"]=" CONFIG=V4096Ara2LaneShuttleConfig USE_ARA=1"
+mapping["chipyard-shuttleara"]=" CONFIG=V4096Ara2LaneShuttleConfig USE_ARA=1 verilog"
 
 mapping["constellation"]=" SUB_PROJECT=constellation"
 mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig"

diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
@@ -145,11 +145,12 @@ case $1 in
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
         ;;
     chipyard-shuttleara)
-        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
+        # Ara does not work with verilator
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
         # Ara cannot run strcmp
         # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1
-        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
-        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
         ;;
     tracegen)
         run_tracegen

diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
@@ -844,29 +844,6 @@ jobs:
           group-key: "group-accels"
           project-key: "chipyard-shuttlevector"
 
-  chipyard-shuttleara-run-tests:
-    name: chipyard-shuttleara-run-tests
-    needs: prepare-chipyard-accels
-    runs-on: as4
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-accels"
-          project-key: "chipyard-shuttleara"
-
   chipyard-gemmini-run-tests:
     name: chipyard-gemmini-run-tests
     needs: prepare-chipyard-accels
@@ -1259,7 +1236,6 @@ jobs:
             chipyard-rerocc-run-tests,
             chipyard-rocketvector-run-tests,
             chipyard-shuttlevector-run-tests,
-            chipyard-shuttleara-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
             chipyard-prefetchers-run-tests,

diff --git a/docs/Generators/Ara.rst b/docs/Generators/Ara.rst
@@ -9,6 +9,8 @@ Example Ara configurations are listed in ``generators/chipyard/src/main/scala/co
 
 To compile simulators using Ara, you must pass an additional ``USE_ARA`` flag to the makefile.
 
+.. Note:: Ara only supports VCS for simulation
+
 .. code-block:: shell
 
      make CONFIG=V4096Ara2LaneRocketConfig USE_ARA=1