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For FireSim, support FIRRTL2 bridge + Chisel 6 annos
- All targets now compile w/ Chisel6 - Remove Chisel3 references as much as possible
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,35 @@ | ||
package firechip.core.firesim | ||
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import firrtl.{AnnotationSeq} | ||
import firrtl.options.{StageMain, Phase, Dependency, StageOptions} | ||
import firrtl.options.Viewer.view | ||
import chipyard.stage._ | ||
import chipyard.stage.phases.{PreservesAll} | ||
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object Generator extends StageMain(new FireSimStage) | ||
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class FireSimStage extends ChipyardStage { | ||
override def extraPostPhases = Seq(Dependency[LegacyFirrtl2Emission]) | ||
} | ||
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final class LegacyFirrtl2Emission extends Phase with PreservesAll with HasChipyardStageUtils { | ||
override val prerequisites = Seq(Dependency[chipyard.stage.ChipyardChiselStage]) | ||
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override def transform(annotations: AnnotationSeq): AnnotationSeq = { | ||
val targetDir = view[StageOptions](annotations).targetDir | ||
val fileName = s"${view[ChipyardOptions](annotations).longName.get}.sfc.fir" | ||
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val annos = annotations.filterNot(_.isInstanceOf[firrtl.options.TargetDirAnnotation]) | ||
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val converted = firrtl2.bridge.ChiselBridge.annosToState(annos) | ||
val emitter = new firrtl2.ChirrtlEmitter | ||
val circuit = converted.copy(annotations = converted.annotations ++ Seq( | ||
firrtl2.EmitCircuitAnnotation(classOf[firrtl2.ChirrtlEmitter]) | ||
)) | ||
val emitted = emitter.execute(circuit) | ||
val emittedCircuit = emitted.annotations.collectFirst { case firrtl2.EmittedFirrtlCircuitAnnotation(circuit) => circuit }.get | ||
writeOutputFile(targetDir, fileName, emittedCircuit.value) | ||
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annotations | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -1,3 +1,6 @@ | ||
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "2.1.1") | ||
addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4") | ||
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.6") | ||
addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "1.1.1") | ||
addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2") | ||
addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.11.0") |
Submodule firesim
updated
7 files
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66 changes: 0 additions & 66 deletions
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tools/stage-chisel3/src/main/scala/ChipyardAnnotations.scala
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