Merge pull request #481 from acceleratedtech/jwise/ti180-soj

efinix: add spiOverJtag support for Ti180J484

doc/FPGAs.yml

@@ -39,7 +39,9 @@ Efinix:
     Flash: OK
 
   - Description: Titanium
-    Model: Ti60
+    Model:
+      - Ti60
+      - Ti180
     URL: https://www.efinixinc.com/products-titanium.html
     Memory: NA
     Flash: OK

doc/boards.yml

@@ -981,3 +981,10 @@
   FPGA: xc7s50csga324?
   Memory: OK
   Flash: OK
+
+- ID: efinix_jtag_ft2232
+  Description: Efinix FT2232 development boards with JTAG on port 2 (Ti180J484 EVK, etc)
+  URL: https://www.efinixinc.com/products-devkits-titaniumti180j484.html
+  FPGA: Titanium Ti180J484 (and others)
+  Memory: OK
+  Flash: NA

spiOverJtag/Makefile

@@ -24,7 +24,7 @@ ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
 	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
 
-EFINIX_PARTS := t8f81 t13f256
+EFINIX_PARTS := t8f81 t13f256 ti180j484
 EFINIX_BIT_FILES := $(addsuffix .bit.gz, $(addprefix spiOverJtag_efinix_, $(EFINIX_PARTS)))
 
 BIT_FILES := $(ALTERA_BIT_FILES) $(EFINIX_BIT_FILES) $(XILINX_BIT_FILES)

spiOverJtag/efinix_build.py

@@ -48,6 +48,17 @@
             "ss_n": "K3", "cclk": "K2", "cdi0": "J1", "cdi1": "J2", "cdi2": "F1", "cdi3": "G2",
         },
     },
+    "Titanium": {
+        "J484": { # ti180, ...
+            "ss_n": "E2", "cclk": "J2", "cdi0": "G2", "cdi1": "H2", "cdi2": "F3", "cdi3": "G3",
+        },
+    },
+}
+
+timing_models = {
+    "T8F81": "C2",
+    "T13F256": "C3",
+    "TI180J484": "C3",
 }
 
 def gen_isf_constr(gateware_name, build_path, device_name, family, pkg):
@@ -110,7 +121,7 @@ def gen_isf_constr(gateware_name, build_path, device_name, family, pkg):
     device        = args.device.upper()
     build_name    = "efinix_spiOverJtag"
     build_dir     = os.path.join(curr_path, f"tmp_efinix_{device.lower()}")
-    timing_model  = "C2" # FIXME: always usable (trion / titanium) ?
+    timing_model  = timing_models.get(device, "C3")
     sources       = [
         {
             'name': os.path.join(curr_path, "efinix_spiOverJtag.v"),

src/efinix.cpp

@@ -228,11 +228,33 @@ void Efinix::program(unsigned int offset, bool unprotect_flash)
 	delete bit;
 }
 
+bool Efinix::detect_flash()
+{
+	if (_jtag) {
+		return SPIInterface::detect_flash();
+	}
+
+#if 0
+	/* Untested logic in SPI path -- if you test this, and it works,
+	 * uncomment it and submit a PR!  */
+	_spi->gpio_clear(_rst_pin);
+
+	bool rv = reinterpret_cast<SPIInterface *>(_spi)->detect_flash();
+
+	reset();
+
+	return rv;
+#else
+	printError("detect flash not supported");
+	return false;
+#endif
+}
+
 bool Efinix::dumpFlash(uint32_t base_addr, uint32_t len)
 {
-	if (!_spi) {
-		printError("jtag: dumpFlash not supported");
-		return false;
+	if (_jtag) {
+		SPIInterface::set_filename(_filename);
+		return SPIInterface::dump(base_addr, len);
 	}
 
 	uint32_t timeout = 1000;
@@ -251,7 +273,7 @@ bool Efinix::dumpFlash(uint32_t base_addr, uint32_t len)
 		return false;
 	}
 
-	/* release SPI access */
+	/* release SPI access.  XXX later: refactor to use reset() and make sure the behavior is the same */
 	_spi->gpio_set(_rst_pin | _oe_pin);
 	usleep(12000);
 

src/efinix.hpp

@@ -28,6 +28,7 @@ class Efinix: public Device, SPIInterface {
 		~Efinix();
 
 		void program(unsigned int offset, bool unprotect_flash) override;
+		bool detect_flash() override;
 		bool dumpFlash(uint32_t base_addr, uint32_t len) override;
 		bool protect_flash(uint32_t len) override {
 			(void) len;