Add Support for Xilinx KCU116 (#322)

* initial kcu116 support

* add kintex ultrascale plus family to xilinx.cpp

* add docs

* combine xcku and xcvu check

* rebuild bitstream for -1 speedgrade

doc/boards.yml

@@ -725,3 +725,10 @@
   FPGA: Virtex UltraScale+ xcvu37p-fsvh2892
   Memory: OK
   Flash: OK
+
+- ID: kcu116
+  Description: Xilinx KCU116
+  URL: https://www.xilinx.com/products/boards-and-kits/kcu116.html
+  FPGA: Kintex UltraScale+ xcku5p-ffvb676
+  Memory: OK
+  Flash: OK

doc/vendors/xilinx.rst

@@ -97,7 +97,7 @@ File load:
   device/package format is something like xc7a35tcsg324 (arty model).
   See :ghsrc:`src/board.hpp <src/board.hpp>`, or :ghsrc:`spiOverJtag <spiOverJtag>` directory for examples.
 
-Some boards with UltraScale FPGAs, like the VCU118, support the SPIx8 (Dual Quad SPI) configuration.
+Some boards with UltraScale FPGAs, like the VCU118 and KCU16, support the SPIx8 (Dual Quad SPI) configuration.
 In this case, the ``spix8`` option ``write_cfgmem`` on the above example can be used to generate two ``.mcs`` files,
 to fit bigger designs or for faster programming. Only ``.mcs`` files can be used to program the FPGA in this case.
 

spiOverJtag/Makefile

@@ -8,6 +8,7 @@ XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx
 	xc7k160tffg676 \
 	xc7k325tffg676 xc7k325tffg900 \
 	xc7k420tffg901 \
+	xcku5p-ffvb676 \
 	xcvu9p-flga2104 xcvu37p-fsvh2892
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 

spiOverJtag/build.py

@@ -55,8 +55,8 @@
     family = "Spartan3E"
     tool = "ise"
     speed = -4
-elif subpart == "xcvu":
-    family = "Virtex UltraScale"
+elif subpart in ["xcvu", "xcku"]:
+    family = "Xilinx UltraScale"
     tool = "vivado"
 else:
     print("Error: unknown device")
@@ -92,6 +92,7 @@
         "xc7s50csga324"    : "xc7s_csga324",
         "xcvu9p-flga2104" : "xcvu9p_flga2104",
         "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
+        "xcku5p-ffvb676" : "xcku5p_ffvb676",
         }[part]
     if tool == "ise":
         cst_type = "UCF"
@@ -126,9 +127,9 @@
                 }
     else:
         cst_type = "xdc"
-        if family == "Virtex UltraScale":
-            tool_options = {'part': part + '-1-e'}
-            if part == "xcvu9p-flga2104":
+        if family == "Xilinx UltraScale":
+            if part in ["xcvu9p-flga2104", "xcku5p-ffvb676"]:
+                tool_options = {'part': part + '-1-e'}
                 parameters["secondaryflash"]= {
                     'datatype': 'int',
                     'paramtype': 'vlogdefine',

spiOverJtag/constr_xcku5p_ffvb676.xdc

@@ -0,0 +1,19 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+# Table 1-2 from UG570
+set_property CFGBVS GND [current_design]
+
+# Primary QSPI flash
+# Connection done through the STARTUPE3 block
+
+# Secondary QSPI flash
+set_property PACKAGE_PIN N23       [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65
+set_property IOSTANDARD  LVCMOS18  [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65
+set_property PACKAGE_PIN P23       [get_ports "sdo_sec_dq1"] ;# Bank  65 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_D05_65
+set_property IOSTANDARD  LVCMOS18  [get_ports "sdo_sec_dq1"] ;# Bank  65 VCCO - VCC1V8   - IO_L22N_T3U_N7_DBC_AD0N_D05_65
+set_property PACKAGE_PIN R20       [get_ports "wpn_sec_dq2"] ;# Bank  65 VCCO - VCC1V8   - IO_L21P_T3L_N4_AD8P_D06_65
+set_property IOSTANDARD  LVCMOS18  [get_ports "wpn_sec_dq2"] ;# Bank  65 VCCO - VCC1V8   - IO_L21P_T3L_N4_AD8P_D06_65
+set_property PACKAGE_PIN R21       [get_ports "hldn_sec_dq3"] ;# Bank  65 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_D07_65
+set_property IOSTANDARD  LVCMOS18  [get_ports "hldn_sec_dq3"] ;# Bank  65 VCCO - VCC1V8   - IO_L21N_T3L_N5_AD8N_D07_65
+set_property PACKAGE_PIN U22       [get_ports "csn_sec"] ;# Bank  65 VCCO - VCC1V8   - IO_L2N_T0L_N3_FWE_FCS2_B_65
+set_property IOSTANDARD  LVCMOS18  [get_ports "csn_sec"] ;# Bank  65 VCCO - VCC1V8   - IO_L2N_T0L_N3_FWE_FCS2_B_65

src/board.hpp

@@ -215,6 +215,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("zc706",           "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zcu102",          "xczu9egffvb1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zcu106",          "xczu7evffvc1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("kcu116",          "xcku5p-ffvb676", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zedboard",        "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zybo_z7_10",      "xc7z010clg400",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zybo_z7_20",      "xc7z020clg400",  "digilent", 0, 0, CABLE_DEFAULT)

src/mcsParser.cpp

@@ -43,6 +43,7 @@ int McsParser::parse()
 {
 	string str;
 	istringstream lineStream(_raw_data);
+	_bit_data.resize(_file_size);
 
 	while (std::getline(lineStream, str, '\n')) {
 		char *ptr;

src/part.hpp

@@ -65,6 +65,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},
 	{0x23731093, {"xilinx", "zynq",     "xc7z045", 6}},
 
+	{0x04a62093, {"xilinx", "kintexusp", "xcku5p", 6}},
 	{0x04A64093, {"xilinx", "artixusp", "xcau25p", 6}},
 
 	{0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 18}},

src/xilinx.cpp

@@ -59,7 +59,8 @@ static std::map<std::string, std::map<std::string, std::vector<uint8_t>>>
 			"default",
 			{
 				{ "USER1",       {0x02} },
-				{ "CFG_IN",      {0x05}},
+				{ "USER2",       {0x03} },
+				{ "CFG_IN",      {0x05} },
 				{ "USERCODE",    {0x08} },
 				{ "IDCODE",      {0x09} },
 				{ "ISC_ENABLE",  {0x10} },
@@ -169,7 +170,7 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_secondary_file_extension = secondary_filename.substr(
 			secondary_filename.find_last_of(".") + 1);
 		_mode = Device::SPI_MODE;
-		if (_device_package != "xcvu9p-flga2104") {
+		if (!(_device_package == "xcvu9p-flga2104" || _device_package == "xcku5p-ffvb676")) {
 			throw std::runtime_error("Error: secondary flash unavailable");
 		}
 	}
@@ -198,6 +199,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_fpga_family = KINTEX_FAMILY;
 	} else if (family == "kintexus") {
 		_fpga_family = KINTEXUS_FAMILY;
+	} else if (family == "kintexusp") {
+		_fpga_family = KINTEXUSP_FAMILY;
 	} else if (family == "artixusp") {
 		_fpga_family = ARTIXUSP_FAMILY;
 	} else if (family == "virtexusp") {

src/xilinx.hpp

@@ -161,6 +161,7 @@ class Xilinx: public Device, SPIInterface {
 			ARTIX_FAMILY,
 			KINTEX_FAMILY,
 			KINTEXUS_FAMILY,
+			KINTEXUSP_FAMILY,
 			ZYNQ_FAMILY,
 			ZYNQMP_FAMILY,
 			XCF_FAMILY,