feat(D1): add builders for DMAC descriptors (#284)

Currently, the DMAC descriptor configuration fields are bit-packed every time a descriptor is constructed. However, the drivers which use DMA always construct descriptors with the same configuration bitfields -- only the addresses and lengths change. We can make this more efficient by constructing the config field once and copying it into each new descriptor. This branch replaces the existing `DescriptorConfig` struct with a `DescriptorBuilder`, which is basically the same thing except it actually constructs the bitfields as single `u32`s, which can then just be copied into a final `Descriptor` for each DMA op. I used `mycelium-bitfield` to do this --- mostly for fun, but it's maybe a bit more readable than the previous code? I dunno. Using the builder, we are able to pack all the configuration fields that don't change a single time. Both of the DMA operations currently run by our SPI and UART drivers always use the same destination addresses, so we're also able to only pack that a single time. Now, only the length and source address have to be re-packed for each new DMA transfer that's started by these drivers. The builder also allows us to avoid some unrepresentable or inconsistent states. We now have builder methods that take source and destination slices and registers, and automatically set the `AddressMode` to `Linear` when the source/dest is a slice, or to `Io` when it's a register. When a slice operand is used, we're also able to set the byte counter to the length of the slice (or the minimum of two slice lengths, when both operands are slices), and set the DRQ type to `Dram` for that operand. Furthermore, I've added additional validation when constructing descriptors.
tosc-rs · Sep 20, 2023 · 1df4a06 · 1df4a06
1 parent ba81b09
commit 1df4a06
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diff --git a/Cargo.lock b/Cargo.lock
diff --git a/platforms/allwinner-d1/Cargo.toml b/platforms/allwinner-d1/Cargo.toml
@@ -12,7 +12,7 @@ repository = "https://github.com/tosc-rs/mnemos"
 homepage = "https://mnemos.dev"
 readme = "./README.md"
 license = "MIT OR Apache-2.0"
-forced-target = "riscv64imac-unknown-none-elf"
+default-target = "riscv64imac-unknown-none-elf"
 
 [lib]
 test = false

diff --git a/platforms/allwinner-d1/d1-core/Cargo.toml b/platforms/allwinner-d1/d1-core/Cargo.toml
@@ -17,6 +17,7 @@ sharp-display = []
 [dependencies]
 serde = { version = "1.0.178", features = ["derive"], default-features = false }
 mnemos-bitslab = { path = "../../../source/bitslab" }
+mycelium-bitfield = "0.1.3"
 
 d1-pac = "0.0.31"
 critical-section = "1.1.1"
@@ -41,4 +42,8 @@ version = "0.7.1"
 [dependencies.futures]
 version = "0.3.21"
 features = ["async-await"]
-default-features = false
+default-features = false
+
+[dev-dependencies]
+proptest = "1"
+proptest-derive = "0.4.0"
diff --git a/platforms/allwinner-d1/d1-core/proptest-regressions/dmac/descriptor.txt b/platforms/allwinner-d1/d1-core/proptest-regressions/dmac/descriptor.txt
@@ -0,0 +1,7 @@
+# Seeds for failure cases proptest has generated in the past. It is
+# automatically read and these particular cases re-run before any
+# novel cases are generated.
+#
+# It is recommended to check this file in to source control so that
+# everyone who runs the test benefits from these saved cases.
+cc 4f86fc0f074d90d51a18ecfed5bace9a7d75c234378f2ff334584ffb761abe86 # shrinks to cfg = ArbitraryConfig { src_drq_type: Sram, src_block_size: Byte1, src_addr_mode: LinearMode, src_data_width: Bit8, dest_drq_type: Sram, dest_block_size: Byte1, dest_addr_mode: LinearMode, dest_data_width: Bit16, bmode_sel: Normal }