Simple safe lock mechanism written in SystemVerilog.
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Feb 14, 2020 - SystemVerilog
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xilinx-vivado
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An FPGA implementation of Cummings' Asynchronous FIFO
fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level
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Apr 14, 2022 - SystemVerilog
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level
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Dec 13, 2024 - SystemVerilog
Restricted Instruction Set Computer (V5) OTTER architecture for Xilinx Basys3 Board. Developed using Xilinx Vivado Suite
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May 7, 2021 - SystemVerilog
the module is also known as sigma delta
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Aug 30, 2022 - SystemVerilog
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