System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
-
Updated
Jul 10, 2024 - C++
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
16-bit CPU written in SystemVerilog
Add a description, image, and links to the verilator-testbench topic page so that developers can more easily learn about it.
To associate your repository with the verilator-testbench topic, visit your repo's landing page and select "manage topics."