Skip to content
#

uart-receiver

Star

Here are 2 public repositories matching this topic...

Language: SystemVerilog
Filter by language
All 13 C++ 3 Verilog 3 SystemVerilog 2 VHDL 2 C 1 HTML 1 Python 1

TahirZia-1 / UART

Star 0

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

simulation rtl verilog vivado uart systemverilog uart-verilog fpga-soc testbench verilog-hdl fpga-board vivado-hls nexys4ddr verilog-project uart-transmitter uart-receiver fpga-programming vivado-simulator
  • Updated Feb 28, 2025
  • SystemVerilog

Improve this page

Add a description, image, and links to the uart-receiver topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the uart-receiver topic, visit your repo's landing page and select "manage topics."

Learn more