6T SRAM memory cell design and analysis using LTspice. Calculated noise margin, conducted Vdd scaling analysis, and analyzed Data Retention Voltage parameter for design optimization.
-
Updated
Mar 26, 2024 - Python
6T SRAM memory cell design and analysis using LTspice. Calculated noise margin, conducted Vdd scaling analysis, and analyzed Data Retention Voltage parameter for design optimization.
Add a description, image, and links to the tradeoff-analysis topic page so that developers can more easily learn about it.
To associate your repository with the tradeoff-analysis topic, visit your repo's landing page and select "manage topics."