This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.
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Updated
Dec 24, 2024 - SystemVerilog
This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.
This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.
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