Script to test single core stability, e.g. for PBO & Curve Optimizer on AMD Ryzen or overclocking/undervolting on Intel processors

This repository contains a fully functional RV32I single-cycle processor core implemented in Verilog. The design is modular, easy to understand, and ideal for students, hobbyists, or anyone looking to learn about RISC-V CPU design, computer architecture, or RTL development. Includes testbench support and Quartus project files for FPGA deployment.