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A-framework-for-developing-Neural-Networks-in-hardware-accelerators

georgevangelou / A-framework-for-developing-Neural-Networks-in-hardware-accelerators

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This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.

hls thesis lenet hdl ristretto vivado-hls
  • Updated May 6, 2022
  • C

n-roussos / A-framework-for-developing-Neural-Networks-in-hardware-accelerators

Star 5

This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.

machine-learning zynq keras neural-networks hardware-acceleration ristretto vivado-hls lenet-mnist fpga-programming
  • Updated Feb 6, 2024
  • C

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