RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set
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Jan 14, 2021
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risc-vcore
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EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and imp…
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Jul 19, 2021 - VHDL
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