A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog
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Updated
Nov 12, 2023 - SystemVerilog
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pipelined-processor
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Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
python processor-architecture analysis assembly lab university-project computer-architecture system-verilog armv8 quartus hardware-description-language processor-design pipelined-processor famaf-unc
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Updated
Jul 23, 2024 - SystemVerilog
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