Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog an…

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)

A RiscV verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD

Xilinx FPGA loader

Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU

Softcore microcontroller with peripherals based on PicoRV32

Wrapper module for the PicoSoC to support the Digilent Basys 3

SoC of PicoRV32i

Minimal system project with riscv core picorv32 : asm startup + linker script + c example + verilog system + testbench + Makefile

Simple implementation of SOC around PicoRV32 soft core.