Simple UVM phase jumping
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Feb 6, 2020 - SystemVerilog
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microelectronics
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4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
design pipeline digital hardware electronics processor vivado systemverilog risc 16-bit integrated-circuits microelectronics
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Apr 23, 2024 - SystemVerilog
Exercício 02 de SystemVerilog
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Dec 8, 2016 - SystemVerilog
Execício 1 de SystemVerilog
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Nov 19, 2016 - SystemVerilog
MD5 hash generator
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Sep 27, 2018 - SystemVerilog
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
design communication-protocol digital hardware electronics receiver vivado uart systemverilog integrated-circuits serial-communication microelectronics
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Apr 23, 2024 - SystemVerilog
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