FPGA-based Sobel Filter Edge Detection
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Updated
Jul 13, 2025 - Verilog
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line-buffer
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VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.
mux comparator seven-segment traffic-light-controller chip-design digtial-design adder-circuit line-buffer ring-counter four-digit-seven-segment-driver
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Updated
May 30, 2022 - VHDL
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