half-adder

Here are 4 public repositories matching this topic...

imvickykumar999 / Logical-Redstone-Reloaded

Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/

world ram binary memory clock cycle redstone ticks rom minecraft-resourcepack flip-flop half-adder latch combinational-circuit full-adder sequential-circuit full-subtractor half-subtractor

Updated Aug 20, 2023
Python

daedalus / bitlogicemu

Star

bitwise operation examples

Updated Nov 27, 2023
Python

A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz

systemverilog half-adder full-adder vyges vyges-ip

Updated Aug 11, 2025
Python

senavs / BitJoy

Star

✔️ Bit, Bytes and Logical Gates Abstraction

python binary pypi bytes bit bits abstraction logic-gates adder half-adder logical-circuits full-adder binary-options pypi-package

Updated Feb 23, 2020
Python

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