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floating-point-adder

Here are 5 public repositories matching this topic...

PaletiKrishnasai / Computer-Architecture

Hardware designs modelled with verilog

cache verilog hardware-designs computer-architecture floating-point-multiplication register-file floating-point-adder pipelined-risc logic-unit

Updated Mar 9, 2021
Verilog

Howeng98 / FloatingPointAdder

floating point adder

verilog verilog-hdl computer-organization floating-point-addition floating-point-adder

Updated Jun 12, 2019
Verilog

DoniaGameel / Verilog-adders-with-synthesis-using-Oasys

explore different implementations of adders and study their characteristics.

carry-look-ahead-adder floating-point-adder oasys ripple-carry-adder carry-save-adder carry-select-adder carry-skip-adder carry-increment-adder carry-bypass-adder

Updated May 23, 2024
Verilog

Stenardt-9002 / Verilog-files-VLSI-course-

verilog files

verilog wallace-tree-multiplier floating-point-multiplication floating-point-adder recursion-doubling testbench-generator-verilog

Updated Jun 22, 2020
Verilog

ArindamSharma / Floating-Point-Adder-Verilog-

Half Precision Floating Point Adder in Verilog

verilog floating-point-adder

Updated Feb 9, 2020
Verilog

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