chisel

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Complete simulation environment for SiFive freedom RISCV CPU platforms

cpu chisel riscv verilog rocketchip

An RTL-level, verified timing accurate DRAM simulator model for the Chisel ecosystem. Simulate memories ranging from HBM to DDR5.

memory chisel dram

Test enviroment to connect jigsaw devices w/ Ibex core in CHISEL & compile the design w/ CIRCT IR to analyze the dumped SV

chisel chisel3 ibex

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