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Language: Verilog
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maarizalmamun / hardware-img-decomp-algo

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This project utilizes a Verilog Register Transfer Level hardware implementation to convert compressed bitstream data to its original uncompressed 320x240 pixel image. This project involves interfacing with various controllers (eg. VGA, UART), developing a state table to establish Finite State Machines to load data, perform matrix multiplication,…

algorithm fpga image-processing fourier-transform verilog-project bitstreams
  • Updated Sep 21, 2020
  • Verilog

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