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1. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

   SystemVerilog

2. edalize edalize Public

   Forked from olofk/edalize

   An abstraction library for interfacing EDA tools

   Python

3. opentitan opentitan Public

   Forked from lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   SystemVerilog

4. riscv-compliance riscv-compliance Public

   Forked from riscv-non-isa/riscv-arch-test

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5. riscv-dv riscv-dv Public

   Forked from chipsalliance/riscv-dv

   SV/UVM based instruction generator for RISC-V processor verification

   SystemVerilog

6. map map Public

   Forked from sparcians/map

   Modeling Architectural Platform

   C++