Support nested software pipelining #463
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vinx13
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* upd * normalize * fix * upd * upd * upd * Readd instruction SampleShapeGenericTiles (#459) * [Backport] MatchBuffer, BufferLocator & GetBlockReadWriteRegion (#460) * [TensorIR] Support for match_buffer from subregion (#8585) Co-authored-by: Junru Shao <junrushao1994@gmail.com> Co-authored-by: Bohan Hou <32121147+spectrometerHBH@users.noreply.github.com> Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com> Co-authored-by: Hongyi Jin <3231950289@qq.com> Co-authored-by: Wuwei Lin <wuwei@apache.org> # Conflicts: # python/tvm/script/special_stmt.py # python/tvm/tir/transform/transform.py # src/tir/analysis/block_access_region_detector.cc # src/tir/analysis/buffer_access_lca_detector.cc # src/tir/transforms/lower_match_buffer.cc # tests/python/integration/test_lower.py # tests/python/unittest/test_tir_analysis_detect_buffer_access_lca.py # tests/python/unittest/test_tir_analysis_get_block_access_region.py # tests/python/unittest/test_tir_lower_match_buffer.py # tests/python/unittest/test_tir_transform_compact_buffer_region.py # tests/python/unittest/test_tvmscript_error_report.py * [TIR] Fix opaque access in buffer locator pass and match_buffer in region detector (#8855) * init * fix * Update src/tir/transforms/plan_update_buffer_allocation_location.cc Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com> * Update src/tir/transforms/plan_update_buffer_allocation_location.cc Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com> * address Co-authored-by: Junru Shao <junrushao1994@gmail.com> Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com> * [TIR] GetBlockReadWriteRegion (#8875) * [TIR] GetBlockReadWriteRegion * Fix black issue * Use constant reference for the interface * Fix lint issue * Catch the correct error class in logical layout test Co-authored-by: Siyuan Feng <hzfengsy@vip.qq.com> Co-authored-by: Junru Shao <junrushao1994@gmail.com> * [BugFix] Fix Conv2d TensorCore Demo (#461) * [Backport] LowerWarpMemory: remove unneeded shuffle when accessing from the same thread (#464) * Lower logical intrin and end-to-end demo (#448) * [WIP] Logical Layout lowering * add intrin * Logical inntrin lowering * e2e demo * LowerLogicalIntrin * Remove num groups * remove old demo * rebase * fix * lower intrin pass * Support nested software pipelining (#463) * Support nested software pipelining * Update test_schedule_software_pipeline.py * upd * upd Co-authored-by: Bojian Zheng <bojian.zheng@mail.utoronto.ca> Co-authored-by: Ruihang Lai <lairuihangdongdong@qq.com> Co-authored-by: Siyuan Feng <hzfengsy@vip.qq.com> Co-authored-by: Junru Shao <junrushao1994@gmail.com> Co-authored-by: Wuwei Lin <wuwei@apache.org>
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