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1. zephyrproject-rtos/zephyr zephyrproject-rtos/zephyr Public

   Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

   C 10.6k 6.5k

2. verilog-to-routing/vtr-verilog-to-routing verilog-to-routing/vtr-verilog-to-routing Public

   Verilog to Routing -- Open Source CAD Flow for FPGA Research

   C++ 1k 388

3. chipsalliance/Surelog chipsalliance/Surelog Public

   SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

   C++ 357 68

4. chipsalliance/sv-tests chipsalliance/sv-tests Public

   Test suite designed to check compliance with the SystemVerilog standard.

   SystemVerilog 286 75

5. f4pga/f4pga-arch-defs f4pga/f4pga-arch-defs Public

   FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

   Jupyter Notebook 270 113

6. hdl/conda-eda hdl/conda-eda Public

   Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.

   Shell 94 27