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TinyFPGA_BX: use nextpnr-ice40
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osresearch committed Jan 18, 2019
1 parent 28a72be commit 84959e7
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Showing 2 changed files with 46 additions and 11 deletions.
12 changes: 9 additions & 3 deletions boards/TinyFPGA_BX/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -27,10 +27,16 @@ all: $(PROJ).rpt fw.bin
%.blif: %.v ../../common/*.v
yosys -q -p 'synth_ice40 -top $(PROJ) -blif $@' $^

%.asc: $(PIN_DEF) %.blif
NO-%.asc: $(PIN_DEF) %.blif
arachne-pnr -d 8k -P $(PKG) -o $@ -p $^
no-%.asc: $(PIN_DEF) %.json
nextpnr-ice40 -d 8k -P $(PKG) -o $@ -p $^

%.asc: $(PIN_DEF) %.json
nextpnr-ice40 \
--$(DEVICE) \
--package $(PKG) \
--asc $@ \
--pcf $(PIN_DEF) \
--json $(basename $@).json \

%.bin: %.asc
icepack $< $@
Expand Down
45 changes: 37 additions & 8 deletions boards/TinyFPGA_BX/bootloader.v
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ module bootloader (
input pin_29_miso,
output pin_30_cs,
output pin_31_mosi,
output pin_32_sck,
output pin_32_sck
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -52,12 +52,11 @@ module bootloader (
);

reg clk_24mhz;
always @(posedge clk_48mhz) clk_24mhz = !clk_24mhz;

reg clk_12mhz;
always @(posedge clk_48mhz) clk_24mhz = !clk_24mhz;
always @(posedge clk_24mhz) clk_12mhz = !clk_12mhz;

wire clk = clk_12mhz; // half speed clock
wire clk = clk_12mhz; // quarter speed clock

////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -106,9 +105,39 @@ module bootloader (
);

assign pin_pu = 1'b1;
assign pin_usbp = usb_tx_en ? usb_p_tx : 1'bz;
assign pin_usbn = usb_tx_en ? usb_n_tx : 1'bz;
assign usb_p_rx = usb_tx_en ? 1'b1 : pin_usbp;
assign usb_n_rx = usb_tx_en ? 1'b0 : pin_usbn;

wire usb_p_rx_io;
wire usb_n_rx_io;
assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_rx_io;
assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_rx_io;

tristate usbn_buffer(
.pin(pin_usbn),
.enable(usb_tx_en),
.data_in(usb_n_rx_io),
.data_out(usb_n_tx)
);

tristate usbp_buffer(
.pin(pin_usbp),
.enable(usb_tx_en),
.data_in(usb_p_rx_io),
.data_out(usb_p_tx)
);
endmodule

module tristate(
inout pin,
input enable,
input data_out,
output data_in
);
SB_IO #(
.PIN_TYPE(6'b1010_01) // tristatable output
) buffer(
.PACKAGE_PIN(pin),
.OUTPUT_ENABLE(enable),
.D_IN_0(data_in),
.D_OUT_0(data_out)
);
endmodule

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