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Travis-CI should run indent over the C code #60

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mithro opened this issue Sep 18, 2015 · 3 comments
Open

Travis-CI should run indent over the C code #60

mithro opened this issue Sep 18, 2015 · 3 comments
Labels
firmware-cypress-fx2 firmware-softcpu level-infrastructure status-help-wanted type-enhancement
Milestone
Travis Quality Co...

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@mithro
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mithro commented Sep 18, 2015

No description provided.

@shenki
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shenki commented Sep 21, 2015

To provide warnings?

I don't think we should have automatic messing with the formatting of code.

@mithro
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mithro commented Sep 21, 2015

Only code which matches the indent formatting should be allow to be committed.

See gst-switch / gstreamer for how that works.

@mithro
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mithro commented Sep 21, 2015

https://github.com/timvideos/gst-switch/blob/master/Makefile.am#L56

@mithro mithro mentioned this issue Oct 1, 2015
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@mithro mithro modified the milestone: Travis Quality Control Oct 7, 2015
@mithro mithro mentioned this issue May 19, 2017
Closed
cr1901 added a commit to cr1901/HDMI2USB-litex-firmware that referenced this issue Mar 13, 2018
@cr1901 @mithro
Update litex submodules; imports changed, does not compile.
4415ccc 
 * flash_proxies changed from c506426 to a628956
    * a628956 - Merge pull request timvideos#4 from cr1901/more-series7 <Robert Jördens>
    * 8be7e2d - Add new bitstream proxies for devices available as of Vivado 2017.4.1. <William D. Jones>
    * 29d9124 - Add new packages for missing Series 7 family members. <William D. Jones>
    * c1d8007 - Add missing Series 7 family members. <William D. Jones>

 * litedram changed from 13d41f6 to 48bc3cb
    * 48bc3cb - README: add migen dependency <Florent Kermarrec>
    * 697f46a - replace litex.gen imports with migen imports <Florent Kermarrec>
    * bd43fd6 - bump to 0.2.dev <Florent Kermarrec>
    * 45a948d - uniformize litex cores <Florent Kermarrec>
    * 5838953 - modules: add MT47H64M16 <Florent Kermarrec>
    * 57c63c1 - phy/a7ddrphy: make reset_n optional <Florent Kermarrec>
    * ec9ad2f - frontend/dma: add description of fifo_buffered parameter <Florent Kermarrec>

 * liteeth changed from 8fc7161 to 33afda7
    * 33afda7 - README: add migen dependency <Florent Kermarrec>
    * 79a6ba7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c15f089 - bump to 0.2.dev <Florent Kermarrec>
    * c42aa09 - uniformize litex cores <Florent Kermarrec>
    * 4e08d6e - Merge pull request timvideos#13 from felixheld/crc_pythonize <enjoy-digital>
    * 9dcc7bc - mac/crc.py: make crc calculation more pythonic <Felix Held>
    * 2ceaa74 - clarify the comments in mac/crc.py code <Felix Held>

 * litepcie changed from 945963d to 6b147e1
    * 6b147e1 - frontend/dma: add 16 bits control field to descriptors <Florent Kermarrec>
    * 08a4501 - README: add migen dependency <Florent Kermarrec>
    * 6afbd1c - frontend/dma/LitePCIeDMAWriter: switch to next decriptor when sink.last is asserted <Florent Kermarrec>
    * ed0b8a4 - phy/xilinx/7-series: integrate v3.3 files (working for x2) <Florent Kermarrec>
    * d9b8b2a - core/tlp/packetizer: add 128 bits support <Florent Kermarrec>
    * 686da6b - core/tlp/depacketizer: add 128 bits support <Florent Kermarrec>
    * 0724533 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3e38b54 - bump to 0.2.dev <Florent Kermarrec>
    * 96cdfe6 - revert phy to 3.0 and tlp packetizer/depacketizer to fixed 64 bit version (until we investigate the regression) <Florent Kermarrec>
    * d7d9e5f - uniformize litex cores <Florent Kermarrec>
    * 058c493 - phy/xilinx/7-series: update to 3.3 <Florent Kermarrec>
    * 98a2c77 - core/tlp/packetizer: typo <Florent Kermarrec>
    * d8bc19c - phy/s7pciephy: add x4 support (untested) <Florent Kermarrec>
    * 4609a88 - test/model/phy: fix typo <Florent Kermarrec>
    * a058223 - test/test_dma: remove converter parameter <Florent Kermarrec>
    * 525b843 - core/tlp/depacketizer: add 128 bits support (untested) <Florent Kermarrec>
    * 6210998 - core/tlp/packetizer: add 128 bits support (untested) <Florent Kermarrec>
    * 45227fe - example_designs/targets: fix dma target <Florent Kermarrec>
    * 7b5b806 - core/tlp/depacketizer: simplify using NextValue <Florent Kermarrec>

 * litesata changed from af00fa6 to a559afb
    * a559afb - README: add migen dependency <Florent Kermarrec>
    * c1e1341 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * eafaf16 - bump to 0.2.dev <Florent Kermarrec>
    * a6c08ce - uniformize litex cores <Florent Kermarrec>

 * litescope changed from aa44da3 to 9d5e605
    * 9d5e605 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 302a484 - bump to 0.2.dev <Florent Kermarrec>
    * 62c4bdd - uniformize litex cores <Florent Kermarrec>
    * 985585f - __init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports <Florent Kermarrec>

 * liteusb changed from 0b05b6c to 23d6a68
    * 23d6a68 - README: add migen dependency <Florent Kermarrec>
    * 102a751 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3faa9ae - bump to 0.2.dev <Florent Kermarrec>
    * d52cf32 - uniformize litex cores <Florent Kermarrec>

 * litevideo changed from 9907975 to 18b88df
    * 18b88df - input/edid: fix scl polarity <Florent Kermarrec>
    * a3c1984 - README: add migen dependency <Florent Kermarrec>
    * 152b6d7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c96ef9c - bump to 0.2.dev <Florent Kermarrec>
    * 2274b01 - uniformize litex cores <Florent Kermarrec>
    * 50e8ac9 - output/VGAPHY: add missing self.sink.ready.eq(1) <Florent Kermarrec>
    * a7e289a - make split-clocking optional, also make output stage PLLE2 + BUFG <bunnie>
    * 78274ed - input/clocking: fix pix_o issue with spartan6 (will need cleaner fix) <Florent Kermarrec>
    * 61fa158 - Merge pull request timvideos#16 from MaZderMind/fix_hdmi_phy_cls_variable_name <Tim Ansell>
    * 96fdbec - Merge pull request timvideos#15 from bunnie/try_florent_720p <enjoy-digital>
    * a44b5d7 - tweak clocking parameters -- maybe marginally better? <bunnie>
    * 2d81c5b - fix phase relationship between master/slave MMCM <bunnie>
    * 9d99716 - these mods add a second MMCM, to fix the BUFG/BUFIO issue <bunnie>

 * litex changed from 4f272580 to 3e7cc255
    *   3e7cc255 - Merge pull request timvideos#69 from mithro/conda-support <enjoy-digital>
    |\
    | * 3bf50479 - travis: Adding some color. <Tim 'mithro' Ansell>
    | * 083c2613 - travis: Move the conda install into script so it can be folded. <Tim 'mithro' Ansell>
    | * da3189c8 - travis: Making the output more readable. <Tim 'mithro' Ansell>
    | * 12bb3ebf - travis: Build all the SoCs (without gateware). <Tim 'mithro' Ansell>
    | * e65c121a - Adding a travis config which tests the conda environment still works. <Tim 'mithro' Ansell>
    | * 795e8285 - Adding conda environment example. <Tim 'mithro' Ansell>
    |/
    *   ab2a3277 - Merge pull request timvideos#67 from cr1901/vivado-paths <enjoy-digital>
    |\
    | * 2b00b7eb - xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. <William D. Jones>
    * |   db20df49 - Merge pull request timvideos#65 from cr1901/tinyfpga-serial <enjoy-digital>
    |\ \
    | * | e71593d6 - platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it optional via `add_extension`. <William D. Jones>
    * | | fa6b2561 - build/xilinx/platform: fix merge <Florent Kermarrec>
    * | |   87d4af0b - Merge pull request timvideos#66 from cr1901/arty_s7 <Tim Ansell>
    |\ \ \
    | * | | d40c5773 - boards/arty_s7: Fix IOStandard on System Clock. <William D. Jones>
    |/ / /
    * | | 7bd718eb - README: add migen installation to quick start guide <Florent Kermarrec>
    | |/
    |/|
    * | 0332f73a - build/xilinx/vivado: revert toolchain_path <Florent Kermarrec>
    * | 2ff50a88 - build: fix merge <Florent Kermarrec>
    * | 64e4e1ce - build: merge with migen.build 27beffe7 <Florent Kermarrec>
    * | 0edfd9b9 - boards/kcu105: regroup sfp tx and rx <Florent Kermarrec>
    |/
    * c5be6e26 - README: add section for newcomers <Florent Kermarrec>
    * f372e8c8 - README: cleanup <Florent Kermarrec>
    * fb088b79 - README: update, migen is no longer forked <Florent Kermarrec>
    * 1925ba17 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 43164b9a - remove migen fork from litex <Florent Kermarrec>
    * 212e1a70 - bump to 0.2.dev <Florent Kermarrec>
    * 64aa4ae4 - uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC <Florent Kermarrec>
    *   aaf09705 - Merge pull request timvideos#64 from q3k/q3k/axi4lite <enjoy-digital>
    |\
    | * 688f26cc - Change AXI interface and tidy code <Sergiusz Bazanski>
    | * 512ed2b3 - Preliminary AXI4Lite CSR bridge support <Sergiusz Bazanski>
    |/
    *   55fc9d2d - Merge pull request timvideos#60 from q3k/for-upstream/top-level-module-selection <enjoy-digital>
    |\
    | * ef511e7e - Specify top-level module in Lattice Diemond build script. <Sergiusz Bazanski>
    | * ef6c517d - Build top module as 'dut' in Verilator and set it as top-level. <Sergiusz Bazanski>
    *   7b5bd404 - Merge pull request timvideos#57 from rohitk-singh/master <enjoy-digital>
    |\
    | * 75e7f950 - BIOS: Flashboot without main ram <Ewen McNeill>
    * c1450280 - board/targets/nexys4ddr: use MT47H64M16 <Florent Kermarrec>
    * 95ebba42 - boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 <Florent Kermarrec>
    * ee4fa597 - boards: add nexys4ddr <Florent Kermarrec>
    *   2ecd1b06 - Merge pull request timvideos#61 from PaulSchulz/master <enjoy-digital>
    |\
    | * 0ac35300 - Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream <Paul Schulz>
    | * 3ac28ed6 - platform/arty.py: Move Pmod definitions to 'connectors' section. <Paul Schulz>
    * c83ae98b - Merge pull request timvideos#63 from cr1901/arty_s7 <enjoy-digital>
    * 4607e532 - boards/platforms: Add Arty S7 Board. <William D. Jones>

Full submodule status
--
 f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 48bc3cb15d17202a19e621acd83d2733190285b2 litedram (remotes/origin/HEAD)
 33afda74f77f7bafa3e4e19641b9043320c47e4e liteeth (remotes/origin/HEAD)
 6b147e1d120a3a062cf2c85e950d358b39edb8eb litepcie (remotes/origin/HEAD)
 a559afb2c53932f29ecc4cec8aa394d1004377c1 litesata (remotes/origin/HEAD)
 9d5e605df3e5f1d54609acc5a2f10764045127e9 litescope (remotes/origin/HEAD)
 23d6a6840d4276f8d1a7f31bafb8d0aaaecff6d1 liteusb (remotes/origin/HEAD)
 18b88dfee6bf6f4ab55d196747ca00c6c84c2ef2 litevideo (remotes/origin/HEAD)
 3e7cc2554b7dcc578ca86fd881d3523625b888f8 litex (remotes/origin/HEAD)
mithro pushed a commit that referenced this issue Mar 18, 2018
@cr1901 @mithro
Update litex submodules; imports changed, does not compile.
15a01e4 
 * flash_proxies changed from c506426 to a628956
    * a628956 - Merge pull request #4 from cr1901/more-series7 <Robert Jördens>
    * 8be7e2d - Add new bitstream proxies for devices available as of Vivado 2017.4.1. <William D. Jones>
    * 29d9124 - Add new packages for missing Series 7 family members. <William D. Jones>
    * c1d8007 - Add missing Series 7 family members. <William D. Jones>

 * litedram changed from 13d41f6 to 48bc3cb
    * 48bc3cb - README: add migen dependency <Florent Kermarrec>
    * 697f46a - replace litex.gen imports with migen imports <Florent Kermarrec>
    * bd43fd6 - bump to 0.2.dev <Florent Kermarrec>
    * 45a948d - uniformize litex cores <Florent Kermarrec>
    * 5838953 - modules: add MT47H64M16 <Florent Kermarrec>
    * 57c63c1 - phy/a7ddrphy: make reset_n optional <Florent Kermarrec>
    * ec9ad2f - frontend/dma: add description of fifo_buffered parameter <Florent Kermarrec>

 * liteeth changed from 8fc7161 to 33afda7
    * 33afda7 - README: add migen dependency <Florent Kermarrec>
    * 79a6ba7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c15f089 - bump to 0.2.dev <Florent Kermarrec>
    * c42aa09 - uniformize litex cores <Florent Kermarrec>
    * 4e08d6e - Merge pull request #13 from felixheld/crc_pythonize <enjoy-digital>
    * 9dcc7bc - mac/crc.py: make crc calculation more pythonic <Felix Held>
    * 2ceaa74 - clarify the comments in mac/crc.py code <Felix Held>

 * litepcie changed from 945963d to 6b147e1
    * 6b147e1 - frontend/dma: add 16 bits control field to descriptors <Florent Kermarrec>
    * 08a4501 - README: add migen dependency <Florent Kermarrec>
    * 6afbd1c - frontend/dma/LitePCIeDMAWriter: switch to next decriptor when sink.last is asserted <Florent Kermarrec>
    * ed0b8a4 - phy/xilinx/7-series: integrate v3.3 files (working for x2) <Florent Kermarrec>
    * d9b8b2a - core/tlp/packetizer: add 128 bits support <Florent Kermarrec>
    * 686da6b - core/tlp/depacketizer: add 128 bits support <Florent Kermarrec>
    * 0724533 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3e38b54 - bump to 0.2.dev <Florent Kermarrec>
    * 96cdfe6 - revert phy to 3.0 and tlp packetizer/depacketizer to fixed 64 bit version (until we investigate the regression) <Florent Kermarrec>
    * d7d9e5f - uniformize litex cores <Florent Kermarrec>
    * 058c493 - phy/xilinx/7-series: update to 3.3 <Florent Kermarrec>
    * 98a2c77 - core/tlp/packetizer: typo <Florent Kermarrec>
    * d8bc19c - phy/s7pciephy: add x4 support (untested) <Florent Kermarrec>
    * 4609a88 - test/model/phy: fix typo <Florent Kermarrec>
    * a058223 - test/test_dma: remove converter parameter <Florent Kermarrec>
    * 525b843 - core/tlp/depacketizer: add 128 bits support (untested) <Florent Kermarrec>
    * 6210998 - core/tlp/packetizer: add 128 bits support (untested) <Florent Kermarrec>
    * 45227fe - example_designs/targets: fix dma target <Florent Kermarrec>
    * 7b5b806 - core/tlp/depacketizer: simplify using NextValue <Florent Kermarrec>

 * litesata changed from af00fa6 to a559afb
    * a559afb - README: add migen dependency <Florent Kermarrec>
    * c1e1341 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * eafaf16 - bump to 0.2.dev <Florent Kermarrec>
    * a6c08ce - uniformize litex cores <Florent Kermarrec>

 * litescope changed from aa44da3 to 9d5e605
    * 9d5e605 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 302a484 - bump to 0.2.dev <Florent Kermarrec>
    * 62c4bdd - uniformize litex cores <Florent Kermarrec>
    * 985585f - __init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports <Florent Kermarrec>

 * liteusb changed from 0b05b6c to 23d6a68
    * 23d6a68 - README: add migen dependency <Florent Kermarrec>
    * 102a751 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3faa9ae - bump to 0.2.dev <Florent Kermarrec>
    * d52cf32 - uniformize litex cores <Florent Kermarrec>

 * litevideo changed from 9907975 to 18b88df
    * 18b88df - input/edid: fix scl polarity <Florent Kermarrec>
    * a3c1984 - README: add migen dependency <Florent Kermarrec>
    * 152b6d7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c96ef9c - bump to 0.2.dev <Florent Kermarrec>
    * 2274b01 - uniformize litex cores <Florent Kermarrec>
    * 50e8ac9 - output/VGAPHY: add missing self.sink.ready.eq(1) <Florent Kermarrec>
    * a7e289a - make split-clocking optional, also make output stage PLLE2 + BUFG <bunnie>
    * 78274ed - input/clocking: fix pix_o issue with spartan6 (will need cleaner fix) <Florent Kermarrec>
    * 61fa158 - Merge pull request #16 from MaZderMind/fix_hdmi_phy_cls_variable_name <Tim Ansell>
    * 96fdbec - Merge pull request #15 from bunnie/try_florent_720p <enjoy-digital>
    * a44b5d7 - tweak clocking parameters -- maybe marginally better? <bunnie>
    * 2d81c5b - fix phase relationship between master/slave MMCM <bunnie>
    * 9d99716 - these mods add a second MMCM, to fix the BUFG/BUFIO issue <bunnie>

 * litex changed from 4f272580 to 3e7cc255
    *   3e7cc255 - Merge pull request #69 from mithro/conda-support <enjoy-digital>
    |\
    | * 3bf50479 - travis: Adding some color. <Tim 'mithro' Ansell>
    | * 083c2613 - travis: Move the conda install into script so it can be folded. <Tim 'mithro' Ansell>
    | * da3189c8 - travis: Making the output more readable. <Tim 'mithro' Ansell>
    | * 12bb3ebf - travis: Build all the SoCs (without gateware). <Tim 'mithro' Ansell>
    | * e65c121a - Adding a travis config which tests the conda environment still works. <Tim 'mithro' Ansell>
    | * 795e8285 - Adding conda environment example. <Tim 'mithro' Ansell>
    |/
    *   ab2a3277 - Merge pull request #67 from cr1901/vivado-paths <enjoy-digital>
    |\
    | * 2b00b7eb - xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. <William D. Jones>
    * |   db20df49 - Merge pull request #65 from cr1901/tinyfpga-serial <enjoy-digital>
    |\ \
    | * | e71593d6 - platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it optional via `add_extension`. <William D. Jones>
    * | | fa6b2561 - build/xilinx/platform: fix merge <Florent Kermarrec>
    * | |   87d4af0b - Merge pull request #66 from cr1901/arty_s7 <Tim Ansell>
    |\ \ \
    | * | | d40c5773 - boards/arty_s7: Fix IOStandard on System Clock. <William D. Jones>
    |/ / /
    * | | 7bd718eb - README: add migen installation to quick start guide <Florent Kermarrec>
    | |/
    |/|
    * | 0332f73a - build/xilinx/vivado: revert toolchain_path <Florent Kermarrec>
    * | 2ff50a88 - build: fix merge <Florent Kermarrec>
    * | 64e4e1ce - build: merge with migen.build 27beffe7 <Florent Kermarrec>
    * | 0edfd9b9 - boards/kcu105: regroup sfp tx and rx <Florent Kermarrec>
    |/
    * c5be6e26 - README: add section for newcomers <Florent Kermarrec>
    * f372e8c8 - README: cleanup <Florent Kermarrec>
    * fb088b79 - README: update, migen is no longer forked <Florent Kermarrec>
    * 1925ba17 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 43164b9a - remove migen fork from litex <Florent Kermarrec>
    * 212e1a70 - bump to 0.2.dev <Florent Kermarrec>
    * 64aa4ae4 - uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC <Florent Kermarrec>
    *   aaf09705 - Merge pull request #64 from q3k/q3k/axi4lite <enjoy-digital>
    |\
    | * 688f26cc - Change AXI interface and tidy code <Sergiusz Bazanski>
    | * 512ed2b3 - Preliminary AXI4Lite CSR bridge support <Sergiusz Bazanski>
    |/
    *   55fc9d2d - Merge pull request #60 from q3k/for-upstream/top-level-module-selection <enjoy-digital>
    |\
    | * ef511e7e - Specify top-level module in Lattice Diemond build script. <Sergiusz Bazanski>
    | * ef6c517d - Build top module as 'dut' in Verilator and set it as top-level. <Sergiusz Bazanski>
    *   7b5bd404 - Merge pull request #57 from rohitk-singh/master <enjoy-digital>
    |\
    | * 75e7f950 - BIOS: Flashboot without main ram <Ewen McNeill>
    * c1450280 - board/targets/nexys4ddr: use MT47H64M16 <Florent Kermarrec>
    * 95ebba42 - boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 <Florent Kermarrec>
    * ee4fa597 - boards: add nexys4ddr <Florent Kermarrec>
    *   2ecd1b06 - Merge pull request #61 from PaulSchulz/master <enjoy-digital>
    |\
    | * 0ac35300 - Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream <Paul Schulz>
    | * 3ac28ed6 - platform/arty.py: Move Pmod definitions to 'connectors' section. <Paul Schulz>
    * c83ae98b - Merge pull request #63 from cr1901/arty_s7 <enjoy-digital>
    * 4607e532 - boards/platforms: Add Arty S7 Board. <William D. Jones>

Full submodule status
--
 f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 48bc3cb15d17202a19e621acd83d2733190285b2 litedram (remotes/origin/HEAD)
 33afda74f77f7bafa3e4e19641b9043320c47e4e liteeth (remotes/origin/HEAD)
 6b147e1d120a3a062cf2c85e950d358b39edb8eb litepcie (remotes/origin/HEAD)
 a559afb2c53932f29ecc4cec8aa394d1004377c1 litesata (remotes/origin/HEAD)
 9d5e605df3e5f1d54609acc5a2f10764045127e9 litescope (remotes/origin/HEAD)
 23d6a6840d4276f8d1a7f31bafb8d0aaaecff6d1 liteusb (remotes/origin/HEAD)
 18b88dfee6bf6f4ab55d196747ca00c6c84c2ef2 litevideo (remotes/origin/HEAD)
 3e7cc2554b7dcc578ca86fd881d3523625b888f8 litex (remotes/origin/HEAD)
mithro pushed a commit that referenced this issue Nov 17, 2018
@cr1901
Updating submodules.
7da331b 
 * litedram changed from 5b02791 to f36bcff
    * f36bcff - phy/gensdrphy: cleanup/simplify pass <Florent Kermarrec>
    * da06715 - core/bankmachine: typo <Florent Kermarrec>
    * ab0d519 - core: change cba_shift parameter to more explicit address_mapping parameter <Florent Kermarrec>
    * 230ea24 - core: simplify/cleanup pass <Florent Kermarrec>
    * 94b844d - core/frontend: move crossbar to core <Florent Kermarrec>
    * 8d24163 - phy/s7ddrphy: use our own bitslip module in fabric <Florent Kermarrec>
    * 20d7675 - phy/s7ddrphy: add additional_read_latency parameter <Florent Kermarrec>
    * f11506a - examples/litedram_gen: cleanup pins definition <Florent Kermarrec>
    * 75b314c - modules: update K4B2G1646F and use timings from datasheet <Florent Kermarrec>
    * b71ed35 - core/bankmachine: manage tRC <Florent Kermarrec>
    * 0abb3e4 - modules: use tRAS and tRP to compute tRC (tRC = tRAS + tRP) <Florent Kermarrec>
    * 9a950f0 - ecc: update core/test <Florent Kermarrec>
    * 8a0d0f0 - phy/s7ddrphy: remove hacky bl8 variant (see #60) <Florent Kermarrec>
    * 5fe4868 - modules: add trrd to all ddr3 modules <Florent Kermarrec>
    *   dbfa929 - Merge pull request #59 from enjoy-digital/tRRD_Fix <enjoy-digital>
    |\
    | * 5315d27 - tRRD incorrectly specified <john@csquare.ca>
    |/
    * 167c0c9 - remove partial reordering code in master, keep things in bank_reordering branch. <Florent Kermarrec>
    * 828129e - core/bank_machine: simplify trascon <Florent Kermarrec>
    * 4fa64c8 - core/bankmachine: remove trccon (activate_allowed not used) <Florent Kermarrec>
    * feac98f - core/bankmachine: use tXXDController everywhere (better timings) <John Sully>
    * bce411e - common: move tXXDController to common <John Sully>
    * fef4701 - core/multiplexer: select all ranks on refresh <Florent Kermarrec>
    * 3481d45 - core/multiplexer: fix rank_decoder width <Florent Kermarrec>
    * 3b5a1ff - modules: add K4B1G0446F <Florent Kermarrec>
    * 48c17ce - modules: fix tWTR regression on MT46H32M32 <Florent Kermarrec>
    * ad0a1d4 - modules: improve timings definition (keep retro-compatibility with previous definitions) <Florent Kermarrec>

 * litepcie changed from a09d225 to a8b8048
    * a8b8048 - core/tlp/reordering: increase buffering <Florent Kermarrec>
    * 9578a3c - LICENSE: typo <Florent Kermarrec>
    * b37065c - Merge pull request #13 from enjoy-digital/reordering <enjoy-digital>
    * 62d6217 - core/tlp/reordering: use buffered=True <Florent Kermarrec>
    * 35a4aa8 - core/tlp/reordering: use buffered data fifo to ease timings <Florent Kermarrec>
    * 288c5f9 - core/tlp/reordering: refactor/simplify <Florent Kermarrec>
    * 1f39ee2 - core/tlp/controller: use log2_int everywhere <Florent Kermarrec>

 * litex changed from 6e327cda to 3e189379
    * 3e189379 - boards/targets: add versa ecp55g prjtrellis target (experimental) <Florent Kermarrec>
    * a69197d2 - build/lattice: add initial prjtrellis support <Florent Kermarrec>
    * 397e3c76 - build/lattice/diamond: use bash on linux <Florent Kermarrec>
    * d029cd24 - build/lattice: improve special_overrides names (vendor_family) <Florent Kermarrec>
    *   60665358 - Merge pull request #114 from mithro/xilinx+yosys <enjoy-digital>
    |\
    | *   b200ce99 - Merge branch 'master' into xilinx+yosys <enjoy-digital>
    | |\
    | |/
    |/|
    * |   8c0982a1 - Merge pull request #118 from mithro/uart-sync <enjoy-digital>
    |\ \
    | * | ba0dd572 - uart: Enable buffering the FIFO. <Tim 'mithro' Ansell>
    |/ /
    * | f9167053 - README: improve instructions for litex_sim <Florent Kermarrec>
    * | e3935b48 - build/sim/verilator: don't use THEADS parameters when threads=1 <Florent Kermarrec>
    * | a44181e7 - soc_sdram: update litedram <Florent Kermarrec>
    * | ab6a530a - bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode <Florent Kermarrec>
    * | b8be9545 - build/xilinx/vivado: enable xpm libraries <Florent Kermarrec>
    * | ab8cf3e3 - soc/cores/clock: add margin parameter to create_clkout (default = 1%) <Florent Kermarrec>
    * | 915c2f41 - bios/sdram: improve write/read leveling <Florent Kermarrec>
    * | deffa603 - platforms/kc705: add ddram_dual_rank <Florent Kermarrec>
    * | 10624c26 - bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) <Florent Kermarrec>
    * |   9f083e9b - Merge pull request #116 from stffrdhrn/sim-uart <enjoy-digital>
    |\ \
    | * | 8877dba7 - sim: serial: Send '\r\n' instead of just '\n' <Stafford Horne>
    |  /
    * | d1879215 - cpu_interface: fix select_triple when only one specified <Florent Kermarrec>
    * | 3b27d2ae - soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains <Florent Kermarrec>
    * | 168b07b9 - soc_core: add csr range check <Florent Kermarrec>
    * |   6febb682 - Merge pull request #112 from cr1901/8k-b-evn <enjoy-digital>
    |\ \
    | * | 9a44f08a - build/platforms: Add ice40_hx8k_b_evn from Migen. <William D. Jones>
    |  /
    * |   9cf4ffb3 - Merge pull request #113 from stffrdhrn/litex-trivial <enjoy-digital>
    |\ \
    | * | ff6de429 - Fix help for or1k builds <Stafford Horne>
    | * | dafdb8df - Fix compiler warnings from GCC 8.1 <Stafford Horne>
    |/ /
    * | 2be52054 - build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) <Florent Kermarrec>
    | * ace97624 - build.xilinx: Convert attributes to something Yosys understands. <Tim 'mithro' Ansell>
    | * 78414c05 - xilinx/viviado: Allow yosys for synthesis. <Tim 'mithro' Ansell>
    | * d13ac3b3 - cpu/mor1kx: Adding verilog include directory. <Tim 'mithro' Ansell>
    | * dc7cd757 - build.xilinx: Run `phys_opt_design` and generate timing report. <Tim 'mithro' Ansell>
    |/
    * 948527b0 - cores/cpu: revert vexriscv (it seems there is a regression in last version) <Florent Kermarrec>
    * 15bca453 - targets/sim: fix integrated_main_ram_size when with_sdram <Florent Kermarrec>

 * migen changed from 0.6.dev-173-gd3b875b to 0.6.dev-179-g657c0c7
    * 657c0c7 - class TSTriple: width is the width of the base signal <Staf Verhaegen>
    * 2d62c0c - platforms/ice40_up5k_b_evn: Add I/O connector and some default I/O (including spiflash). <William D. Jones>
    * ea6e483 - Fix issue where BusSynchronizer fails when iclock << oclock <bunnie>
    * 076ec0d - fhdl.visit: fix nondeterminism in visit_Case. <whitequark>
    * 1e114c7 - add a print to show user context when an exception is raised while evaluating a generator yield statement in simulation <N. Engelhardt>
    * ba63364 - platforms/ice40_hx8k_b_evn: Add pins for spiflash io. <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 f36bcff49fe96867503c219dd705ff8d7eb951cd litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a8b804809d84e2125eb603bf9feefc9cef31d22b litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 3e189379f9272ba184fcdcfe077eb139f1f0fc7f litex (heads/master)
 657c0c72e63597162837809dfe3635d69a98cfd9 migen (0.6.dev-179-g657c0c7)
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