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Feature/add 7 segment display #84

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merged 4 commits into from
Aug 16, 2022
Merged

Feature/add 7 segment display #84

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4b4b2c0
Add 1-digit 7 segment display for HEX numbers.
mateusz-sz May 23, 2022
55e50f7
Implement 1 digit 7-segment display.
mateusz-sz Jun 8, 2022
7e8f3ca
Fix a typo.
mateusz-sz Jun 8, 2022
b81628a
Update README.
mateusz-sz Aug 10, 2022
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3 changes: 2 additions & 1 deletion README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -154,6 +154,8 @@ instance.
* Subcircuit output: `Output`
* Attributes: `bits` (natural number)
* Inputs: `in` (`bits`-bit)
* 7 segment display output: `Display7`
* Inputs: `bits` (8-bit only - most significant bit controls decimal point LED)
* Bus grouping: `BusGroup`
* Attributes: `groups` (array of natural numbers)
* Inputs: `in0` (`groups[0]`-bit) ... `inN` (`groups[N]`-bit)
Expand Down Expand Up @@ -187,7 +189,6 @@ Some ideas for further developing the simulator.
* Undo-redo capability.
* Saving and loading circuits, including layout and state.
* Generic handling of negation for unary/binary gates (negation on inputs/outputs) for better clarity.
* Zooming in/out on schematics.
* SVG export.
* Verilog export.
* Smartphone and tablet compatible UI.
Expand Down
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