v1.5

New Features

• Add support for Yggdrasil Decision Forests models by @achoum in #65

Bug Fixes

• Propagate HLS clock period to synthesis scripts @thesps in #64
• Add expression balancing for xilinxhls backend by @francescobrivio in #68
  • significantly reduced latency when using saturation and rounding mode in score type

New Contributors

• @francescobrivio made their first contribution in #68

Full Changelog: v1.4...v1.5

v1.4: Provide interface to add boards. Add option to pass extra build param…

New Features

• Static accelerators: make bitfiles from xilinxhls backend projects #53
• More utilities for model inspection #61
• Vivado synthesis option for xilinxhls backend for better resource estimation #61

Bug Fixes

• Don't pad trees automatically when unroll is False for xilinxhls backend (proper support for sparse trees) #61
• Report reading is more robust in case of missing files #61

Deprecated Features

• vivadohls and vitishls backends are no longer generated dynamically. Only xilinxhls backend remains. Tool discovery is still in place and both Vivado HLS and Vitis HLS remain supported. #61

v1.4-beta.1

What's Changed

• Static Accelerators by @thesps in #53
• Miscellaneous Improvements by @thesps in #61
• Updates to boards/accelerators by @thesps in #62

Full Changelog: v1.3...v1.4-beta.1

v1.3

New Features

• Python backend by @thesps in #55

Bug Fixes

• Fix links in README.md by @Chriisbrown in #59
• CPP backend minor fix by @thesps in #60

Full Changelog: v1.2...v1.3

v1.2

New Features

• Tree and model visualisation with Graphviz PR 48
  

Bug Fixes

• xgboost converter fixes PR 47, issue 23
• Fixes for compilation and prediction on OSX PR 49

Full Changelog: v1.1...v1.2

cypress

New features:

• Forest Processing Unit for fast, reconfigurable BDT inference on FPGAs

cedar

New features:

• Support for TensorFlow Decision Forests
• 'Unrolled' Xilinx HLS optimization for much faster C Synthesis time, enabled by default with Unroll configuration parameter (see performance plots on the PR)
• Synthesis report reading for HLS and VHDL backends: conifer_model.read_report() for models of those backends
• new_config parameter of conifer.model.load_model to override a saved model's configuration (e.g. to change backend or precision)
• Simulator discovery for VHDL backend (use whichever is installed)
• Model metadata saved with model JSON export for provenance tracking - conifer version, model conversion time
• Documentation webpages at https://ssummers.web.cern.ch/conifer/
• Significantly overhauled internal representation

Bug fixes:

• Fix to sklearn converter for newer sklearn versions

v1.0-r0

Bug fixes:

• Fix faulty include on fixed-point emulation for VHDL backend

v1.0-beta.1

New features:

• Support for TensorFlow Decision Forests
• 'Unrolled' Xilinx HLS optimization for much faster C Synthesis time, enabled by default with Unroll configuration parameter (see performance plots on the PR)
• Synthesis report reading for HLS and VHDL backends: conifer_model.read_report() for models of those backends
• new_config parameter of conifer.model.load_model to override a saved model's configuration (e.g. to change backend or precision)
• Simulator discovery for VHDL backend (use whichever is installed)
• Model metadata saved with model JSON export for provenance tracking - conifer version, model conversion time
• Documentation webpages at https://ssummers.web.cern.ch/conifer/
• Significantly overhauled internal representation

Bug fixes:

• Fix to sklearn converter for newer sklearn versions

v0.4

New features:

• Model save/load functionality. model.save() to export a JSON file, conifer.model.load_model(‘my_prj.json’) to load a saved model. The JSON file can also be used for C++ evaluation.
• Better agreement of output predictions between VHDL backend and others using new FixedPointConverter module
• model.build returns success status

Bug fixes:

• Fix crash when writing project to existing directory