Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

Testing the theory that if the interrupt happens during a bank switch
the first read will be blocked and since the interrupts are now
disabled the bank switch will fail as well.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>

We want to make sure the sync_go does happen after the last write

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

Follow the recommended programming flows.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

For some reason, we don't have a symmetry between clock stop and clock
start. We should disable the interrupts first on clock stop, and
re-enable them last on clock restart.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

Follow recommended programming flows.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

Test hypothesis that a delay might help with rate conditions

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

Add the controller and link id to better identify the failure.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

The exclusion between regular and deferred messages doesn't seem quite
right.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

These registers come straight from platform firmware properties, for
integration/debug it's useful to know the values directly from the
kernel logs.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

We need a helper to disable peripheral alerts during bank switchs.

FIXME: cancelling the work locks the system, something is still off

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>

… config

There is an potential deadlock on Intel platforms with the following
scenario:

a) the bank switch starts and the msg->lock is taken

b) an interrupt happens and the workqueue schedules a read from
IntStat0 register, which is blocked by the msg->lock

c) the manager writes the bank switch command, which is blocked by the
read that won't go out.

b) is blocked by a) and c) is blocked by b).

This patch suggests disabling the peripheral interrupts temporarily
during sync_arm/sync_go sequences used by the bank switch.

FIXME: What happens if there's already a work scheduled?

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>