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mmc: dw_mmc: move rockchip related code to a separate file
To support HS200 and UHS-1, we need add a big hunk of code, as shown in the following patches. So a separate file for rockchip SOCs is suitable. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,136 @@ | ||
| /* | ||
| * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License as published by | ||
| * the Free Software Foundation; either version 2 of the License, or | ||
| * (at your option) any later version. | ||
| */ | ||
|
|
||
| #include <linux/module.h> | ||
| #include <linux/platform_device.h> | ||
| #include <linux/clk.h> | ||
| #include <linux/mmc/host.h> | ||
| #include <linux/mmc/dw_mmc.h> | ||
| #include <linux/of_address.h> | ||
|
|
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| #include "dw_mmc.h" | ||
| #include "dw_mmc-pltfm.h" | ||
|
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| #define RK3288_CLKGEN_DIV 2 | ||
|
|
||
| static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr) | ||
| { | ||
| *cmdr |= SDMMC_CMD_USE_HOLD_REG; | ||
| } | ||
|
|
||
| static int dw_mci_rk3288_setup_clock(struct dw_mci *host) | ||
| { | ||
| host->bus_hz /= RK3288_CLKGEN_DIV; | ||
|
|
||
| return 0; | ||
| } | ||
|
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| static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) | ||
| { | ||
| int ret; | ||
| unsigned int cclkin; | ||
| u32 bus_hz; | ||
|
|
||
| /* | ||
| * cclkin: source clock of mmc controller | ||
| * bus_hz: card interface clock generated by CLKGEN | ||
| * bus_hz = cclkin / RK3288_CLKGEN_DIV | ||
| * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) | ||
| * | ||
| * Note: div can only be 0 or 1 | ||
| * if DDR50 8bit mode(only emmc work in 8bit mode), | ||
| * div must be set 1 | ||
| */ | ||
| if (ios->bus_width == MMC_BUS_WIDTH_8 && | ||
| ios->timing == MMC_TIMING_MMC_DDR52) | ||
| cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; | ||
| else | ||
| cclkin = ios->clock * RK3288_CLKGEN_DIV; | ||
|
|
||
| ret = clk_set_rate(host->ciu_clk, cclkin); | ||
| if (ret) | ||
| dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); | ||
|
|
||
| bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; | ||
| if (bus_hz != host->bus_hz) { | ||
| host->bus_hz = bus_hz; | ||
| /* force dw_mci_setup_bus() */ | ||
| host->current_speed = 0; | ||
| } | ||
| } | ||
|
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||
| static const struct dw_mci_drv_data rk2928_drv_data = { | ||
| .prepare_command = dw_mci_rockchip_prepare_command, | ||
| }; | ||
|
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||
| static const struct dw_mci_drv_data rk3288_drv_data = { | ||
| .prepare_command = dw_mci_rockchip_prepare_command, | ||
| .set_ios = dw_mci_rk3288_set_ios, | ||
| .setup_clock = dw_mci_rk3288_setup_clock, | ||
| }; | ||
|
|
||
| static const struct of_device_id dw_mci_rockchip_match[] = { | ||
| { .compatible = "rockchip,rk2928-dw-mshc", | ||
| .data = &rk2928_drv_data }, | ||
| { .compatible = "rockchip,rk3288-dw-mshc", | ||
| .data = &rk3288_drv_data }, | ||
| {}, | ||
| }; | ||
| MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); | ||
|
|
||
| static int dw_mci_rockchip_probe(struct platform_device *pdev) | ||
| { | ||
| const struct dw_mci_drv_data *drv_data; | ||
| const struct of_device_id *match; | ||
|
|
||
| if (!pdev->dev.of_node) | ||
| return -ENODEV; | ||
|
|
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| match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); | ||
| drv_data = match->data; | ||
|
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| return dw_mci_pltfm_register(pdev, drv_data); | ||
| } | ||
|
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| #ifdef CONFIG_PM_SLEEP | ||
| static int dw_mci_rockchip_suspend(struct device *dev) | ||
| { | ||
| struct dw_mci *host = dev_get_drvdata(dev); | ||
|
|
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| return dw_mci_suspend(host); | ||
| } | ||
|
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| static int dw_mci_rockchip_resume(struct device *dev) | ||
| { | ||
| struct dw_mci *host = dev_get_drvdata(dev); | ||
|
|
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| return dw_mci_resume(host); | ||
| } | ||
| #endif /* CONFIG_PM_SLEEP */ | ||
|
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| static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops, | ||
| dw_mci_rockchip_suspend, | ||
| dw_mci_rockchip_resume); | ||
|
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| static struct platform_driver dw_mci_rockchip_pltfm_driver = { | ||
| .probe = dw_mci_rockchip_probe, | ||
| .remove = __exit_p(dw_mci_pltfm_remove), | ||
| .driver = { | ||
| .name = "dwmmc_rockchip", | ||
| .of_match_table = dw_mci_rockchip_match, | ||
| .pm = &dw_mci_rockchip_pmops, | ||
| }, | ||
| }; | ||
|
|
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| module_platform_driver(dw_mci_rockchip_pltfm_driver); | ||
|
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| MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); | ||
| MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension"); | ||
| MODULE_ALIAS("platform:dwmmc-rockchip"); | ||
| MODULE_LICENSE("GPL v2"); |