[dx11] Constant buffer binding and AtomicIncrement in RAND_STATE #4650
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Change the parameter from SNodeTreeManager to SNodeTreeManager*.
1. Change Dx11Pipeline::device_ from a shared_ptr to a raw pointer Previously, Dx11Pipeline::device_ was a shared_ptr. This can cause the device_ to be destructed twice when the program finishes. Because the pipeline is created by Dx11Device::create_pipeline, logically speaking the device owns the pipeline, rather than the pipeline owning the device. So it makes sense if the pipeline is not tracking the life time of its Dx11Device object, thus switching to a raw pointer. 2. Call hlsl.remap_num_workgroups_builtin() This fixes the "RuntimeError: NumWorkgroups builtin is used, but remap_num_workgroups_builtin() was not called. Cannot emit code for this builtin." error. 3. This change also adds a few other Dx11CommandList commands.
It turns out the SPIRV code generator has started to use constant buffers now, and because of this, we must differentiate buffer() and rw_buffer(). With SPIRV-HLSL, buffer() populates constant buffers, while rw_buffer() populates unordered access views (UAVs). This change makes the necessary changes. Tested: can run "laplace.py"
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I just found The slot is not explicitly mentioned with the "register" keyword in the HLSL source (if it does, it will be To compare this is what slot 0 looks like: Adding this allows the I guess I may do some cleanup and add that to this pull request as well since it's not a large change. ================================== Edit: the CB slot for Example: (1) should be b0 b/c the "paint" kernel has no CB. (2) should be b1 b/c the "vector_to_image" kernel uses cb0 |
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bobcao3
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Apr 12, 2022
bobcao3
reviewed
Apr 12, 2022
Previsouly, SPIRV_Cross_NumWorkgroups is fixed at constant buffer 1 (b1). This is not correct and actually should be set to "1 past the CBs used by the kernel", which can be b0 or b1. Tested: Can run "simple_uv.py" and simplified "mpm88.py"
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Previously, init_random_function uses an add operation to increment the pointer to the RNG state. This generates the following HLSL: global_tmps_buffer_u32.Store(4096, global_tmps_buffer_u32.Load(4096) + 1u); The HLSL compiler will complain with the following error: error X3694: race condition writing to shared resource detected, consider making this write conditional. Because of this, we use the atomic addition operation to achieve the same result. The generated HLSL now becomes: uint _67; global_tmps_buffer_u32.InterlockedAdd(4096, 1, _67);
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Related issue = #992
This makes a bit more progress for the dx11 backend, it now runs the mpm88.py program. This change has to deal with a few updates in the Taichi infrastructure:
SPIRV-cross now differentiates read-only buffers (
ResourceBinder::buffer) from read-write buffers (ResourceBinder::rw_buffer) differently, so the backend has to handle Constant Buffers in addition to Unordered Access Views.SPIRV-cross now uses a different set of default options, so the backend needs to call
remap_num_workgroups_builtin.Using
spv::Op::OpAtomicIIncrementfor the random number generator state increment, so that the generated HLSL will not cause the HLSL compiler to generate an errorTested: runs mpm88.py