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ethernet_mac
ethernet_mac PublicForked from yol/ethernet_mac
Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
VHDL
7 contributions in the last year
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Contribution activity
March 2025
Created 1 repository
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svancau/open-logic
VHDL
This contribution was made on Mar 19
Created a pull request in open-logic/open-logic that received 1 comment
Created an issue in open-logic/open-logic that received 4 comments
Disable TMR insertion for CDC
Hello, I'm working on a FPGA that will require Triple modular redundancy inserted during synthesis. I'm planning to add the syn_radhardlevel attrib…
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comments
Opened 1 other issue in 1 repository
open-logic/open-logic
1
closed
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Have blocks with async reset
This contribution was made on Mar 11