Add ZCU208

README.md

@@ -1,11 +1,15 @@
 <img src="strathsdr_banner.png" width="100%">
 
 # StrathSDR RFSoC SD-FEC
-This repository features an RFSoC SD-FEC design that is compatible with [PYNQ image v2.7](https://github.com/Xilinx/PYNQ/releases) for the ZCU111, RFSoC2x2, and RFSoC4x2 development board.
+This repository features an RFSoC SD-FEC design that is compatible with [PYNQ image v2.7](https://github.com/Xilinx/PYNQ/releases) and greater for the following RFSoC development boards:
+* [ZCU208](https://www.xilinx.com/products/boards-and-kits/zcu208.html),
+* [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html),
+* [RFSoC4x2](http://rfsoc-pynq.io/), 
+* [RFSoC2x2](http://rfsoc-pynq.io/).
 
 ## Quick Start
 Follow the instructions below to install the Python package now. **You will need to give your board access to the internet**.
-* Power on your RFSoC development board with an SD Card containing a fresh PYNQ v2.7 image.
+* Power on your RFSoC development board with an SD Card containing a fresh PYNQ v2.7 or greater image.
 * Navigate to Jupyter Labs by opening a browser (preferably Chrome) and connecting to `http://<board_ip_address>:9090/lab`.
 * We need to open a terminal in Jupyter Lab. Firstly, open a launcher window as shown in the figure below:
 
@@ -22,7 +26,7 @@ Follow the instructions below to install the Python package now. **You will need
 Run the code below in the jupyter terminal to install the Python package.
 
 ```sh
-pip3 install git+https://github.com/strath-sdr/rfsoc_sdfec
+pip3 install https://github.com/strath-sdr/rfsoc_sdfec/archive/refs/tags/v1.0.2.tar.gz
 ```
 
 This repository currently has no Jupyter notebooks. See https://github.com/strath-sdr/RFSoC-Book for compatible notebooks.

boards/RFSoC2x2/strath_sdfec/Makefile

@@ -1,10 +1,11 @@
-all: block_design bitstream clean
+all: bitstream
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
 bitstream:
+	$(MAKE) block_design
 	vivado -mode batch -source make_bitstream.tcl -notrace
 
 clean:
-	rm -rf block_design *.jou *.log NA .Xil
+	rm -rf block_design *.jou *.log NA .Xil || true

boards/RFSoC2x2/strath_sdfec/make_bitstream.tcl

@@ -12,7 +12,7 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 2
+launch_runs impl_1 -to_step write_bitstream -jobs 8
 wait_on_run impl_1
 
 # Move and rename bitstream to final location

boards/RFSoC2x2/strath_sdfec_hw/Makefile

@@ -1,10 +1,11 @@
-all: block_design bitstream clean
+all: bitstream
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
 bitstream:
+	$(MAKE) block_design
 	vivado -mode batch -source make_bitstream.tcl -notrace
 
 clean:
-	rm -rf block_design *.jou *.log NA .Xil
+	rm -rf block_design *.jou *.log NA .Xil || true

boards/RFSoC2x2/strath_sdfec_hw/make_bitstream.tcl

@@ -12,7 +12,7 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 2
+launch_runs impl_1 -to_step write_bitstream -jobs 8
 wait_on_run impl_1
 
 # Move and rename bitstream to final location

boards/RFSoC4x2/strath_sdfec/Makefile

@@ -1,10 +1,11 @@
-all: block_design bitstream clean
+all: bitstream
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
 bitstream:
+	$(MAKE) block_design
 	vivado -mode batch -source make_bitstream.tcl -notrace
 
 clean:
-	rm -rf block_design *.jou *.log NA .Xil
+	rm -rf block_design *.jou *.log NA .Xil || true

boards/RFSoC4x2/strath_sdfec/make_bitstream.tcl

@@ -12,7 +12,7 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 2
+launch_runs impl_1 -to_step write_bitstream -jobs 8
 wait_on_run impl_1
 
 # Move and rename bitstream to final location

boards/RFSoC4x2/strath_sdfec_hw/Makefile

@@ -1,10 +1,11 @@
-all: block_design bitstream clean
+all: bitstream
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
 bitstream:
+	$(MAKE) block_design
 	vivado -mode batch -source make_bitstream.tcl -notrace
 
 clean:
-	rm -rf block_design *.jou *.log NA .Xil
+	rm -rf block_design *.jou *.log NA .Xil || true

boards/RFSoC4x2/strath_sdfec_hw/make_bitstream.tcl

@@ -12,7 +12,7 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 2
+launch_runs impl_1 -to_step write_bitstream -jobs 8
 wait_on_run impl_1
 
 # Move and rename bitstream to final location

boards/ZCU111/strath_sdfec/Makefile

@@ -1,10 +1,11 @@
-all: block_design bitstream clean
+all: bitstream
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
 bitstream:
+	$(MAKE) block_design
 	vivado -mode batch -source make_bitstream.tcl -notrace
 
 clean:
-	rm -rf block_design *.jou *.log NA .Xil
+	rm -rf block_design *.jou *.log NA .Xil || true

boards/ZCU111/strath_sdfec/make_bitstream.tcl

@@ -12,7 +12,7 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 2
+launch_runs impl_1 -to_step write_bitstream -jobs 8
 wait_on_run impl_1
 
 # Move and rename bitstream to final location

boards/ZCU111/strath_sdfec_hw/Makefile

@@ -1,10 +1,11 @@
-all: block_design bitstream clean
+all: bitstream
 
 block_design:
 	vivado -mode batch -source make_block_design.tcl -notrace
 
 bitstream:
+	$(MAKE) block_design
 	vivado -mode batch -source make_bitstream.tcl -notrace
 
 clean:
-	rm -rf block_design *.jou *.log NA .Xil
+	rm -rf block_design *.jou *.log NA .Xil || true

boards/ZCU111/strath_sdfec_hw/make_bitstream.tcl

@@ -12,7 +12,7 @@ set_property top ${design_name}_wrapper [current_fileset]
 update_compile_order -fileset sources_1
 
 # Call implement
-launch_runs impl_1 -to_step write_bitstream -jobs 2
+launch_runs impl_1 -to_step write_bitstream -jobs 8
 wait_on_run impl_1
 
 # Move and rename bitstream to final location

boards/ZCU208/strath_sdfec/constraints.xdc

@@ -0,0 +1 @@
+## ZCU208 Constraints

boards/ZCU208/strath_sdfec/make_bitstream.tcl

@@ -0,0 +1,23 @@
+set overlay_name "block_design"
+set design_name "strath_sdfec"
+
+# Open project
+open_project ./${overlay_name}/${overlay_name}.xpr
+open_bd_design ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd
+
+# Add top wrapper and xdc files
+make_wrapper -files [get_files ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top
+add_files -norecurse ./${overlay_name}/${overlay_name}.gen/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.vhd
+set_property top ${design_name}_wrapper [current_fileset]
+update_compile_order -fileset sources_1
+
+# Call implement
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+wait_on_run impl_1
+
+# Move and rename bitstream to final location
+file mkdir ./bitstream
+file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ./bitstream/${design_name}.bit
+
+# copy hwh files
+file copy -force ./${overlay_name}/${overlay_name}.gen/sources_1/bd/${design_name}/hw_handoff/${design_name}.hwh ./bitstream/${design_name}.hwh

boards/ZCU208/strath_sdfec/make_block_design.tcl

@@ -0,0 +1,18 @@
+set overlay_name "block_design"
+set design_name "strath_sdfec"
+set iprepo_dir ./../../ip/iprepo
+
+# Create project
+create_project ${overlay_name} ./${overlay_name} -part xczu48dr-ffvg1517-2-e
+set_property BOARD_PART xilinx.com:zcu208:part0:2.0 [current_project]
+set_property target_language VHDL [current_project]
+
+# Set IP repository paths
+set_property ip_repo_paths $iprepo_dir [current_project]
+update_ip_catalog
+
+# Add constraints
+add_files -fileset constrs_1 -norecurse ./constraints.xdc
+
+# Make block design
+source ./${design_name}.tcl

boards/ZCU208/strath_sdfec/makefile

@@ -0,0 +1,11 @@
+all: bitstream
+
+block_design:
+	vivado -mode batch -source make_block_design.tcl -notrace
+
+bitstream:
+	$(MAKE) block_design
+	vivado -mode batch -source make_bitstream.tcl -notrace
+
+clean:
+	rm -rf block_design *.jou *.log NA .Xil || true