Adding Vitis Unified HLS Python CLI

system_vitis_unified_hls.mk

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+##############################################################################
+## This file is part of 'SLAC Firmware Standard Library'.
+## It is subject to the license terms in the LICENSE.txt file found in the
+## top-level directory of this distribution and at:
+##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+## No part of 'SLAC Firmware Standard Library', including this file,
+## may be copied, modified, propagated, or distributed except according to
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+
+# Detect project name
+export PROJECT = $(notdir $(PWD))
+
+# Detect project path
+export PROJ_DIR = $(abspath $(PWD))
+
+# Project Build Directory ("workspace")
+export OUT_DIR  = $(PROJ_DIR)/build
+
+# Build System Variables
+export VIVADO_VERSION = $(shell vivado -version | grep -Po "v(\d+\.)+\d+" | cut -c2-)
+export RUCKUS_DIR     = $(TOP_DIR)/submodules/ruckus
+
+# Specifies if we need to modify the ip/component.xml to support "all" FPGA family types
+ifndef ALL_XIL_FAMILY
+export ALL_XIL_FAMILY = 1
+endif
+
+include $(TOP_DIR)/submodules/ruckus/system_shared.mk
+
+.PHONY : all
+all: target
+
+###############################################################
+#### Printout Env. Variables ##################################
+###############################################################
+.PHONY : test
+test:
+	@echo VIVADO_VERSION: $(VIVADO_VERSION)
+	@echo PROJECT: $(PROJECT)
+	@echo PROJ_DIR: $(PROJ_DIR)
+	@echo TOP_DIR: $(TOP_DIR)
+	@echo OUT_DIR: $(OUT_DIR)
+	@echo RUCKUS_DIR: $(RUCKUS_DIR)
+	@echo BUILD_STRING: $${BUILD_STRING}
+	@echo GIT_HASH_LONG: $(GIT_HASH_LONG)
+	@echo GIT_HASH_SHORT: $(GIT_HASH_SHORT)
+
+###############################################################
+#### Build Location ###########################################
+###############################################################
+.PHONY : proj
+proj:
+	$(call ACTION_HEADER,"Vitis HLS Create Project")
+	@test -d $(OUT_DIR)     || mkdir $(OUT_DIR)
+	@test -d $(PROJ_DIR)/ip || mkdir $(PROJ_DIR)/ip
+	@cd $(OUT_DIR); vitis -s $(RUCKUS_DIR)/vitis/hls/create_proj.py
+
+###############################################################
+#### Vitis HLS Batch Build Mode ###############################
+###############################################################
+.PHONY : build
+build : proj
+	$(call ACTION_HEADER,"Vitis HLS Build")
+	@cd $(OUT_DIR); vitis -s $(RUCKUS_DIR)/vitis/hls/build.py
+
+###############################################################
+#### Vitis HLS Interactive ####################################
+###############################################################
+.PHONY : interactive
+interactive : proj
+	$(call ACTION_HEADER,"Vitis HLS Interactive")
+	@cd $(OUT_DIR); vitis -i
+
+###############################################################
+#### Vitis HLS Gui ############################################
+###############################################################
+.PHONY : gui
+gui : proj
+	$(call ACTION_HEADER,"Vitis Unified IDE")
+	@cd $(OUT_DIR); vitis -w $(OUT_DIR)
+
+###############################################################
+#### Clean ####################################################
+###############################################################
+.PHONY : clean
+clean:
+	rm -rf $(OUT_DIR)

vitis/hls/build.py

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+#!/usr/bin/env python3
+##############################################################################
+## This file is part of 'SLAC Firmware Standard Library'.
+## It is subject to the license terms in the LICENSE.txt file found in the
+## top-level directory of this distribution and at:
+##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+## No part of 'SLAC Firmware Standard Library', including this file,
+## may be copied, modified, propagated, or distributed except according to
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+
+import vitis
+import os
+import shutil
+import zipfile
+
+# Project variables
+workspace = os.getenv("OUT_DIR")
+comp_name = os.getenv("PROJECT")
+proj_zip  = f'{workspace}/{comp_name}/{comp_name}/{comp_name}.zip'
+build_zip = f'{os.getenv("PROJ_DIR")}/ip/{comp_name}.zip'
+
+# Create a client object
+client = vitis.create_client()
+
+# Set workspace
+client.set_workspace(workspace)
+
+# Set the component
+hls_test_comp = client.get_component(comp_name)
+
+# Run c-simulation on the component
+hls_test_comp.run('C_SIMULATION')
+
+# Run synthesis on the component
+hls_test_comp.run('SYNTHESIS')
+
+# Run co-simulation on the component
+hls_test_comp.run('CO_SIMULATION')
+
+# Run package on the component
+hls_test_comp.run('PACKAGE')
+
+# Close the client connection and terminate the vitis server
+vitis.dispose()
+
+# Check if ALL_XIL_FAMILY is enabled
+if int(os.getenv("ALL_XIL_FAMILY")) > 0:
+
+    # Over the .ZIP file and decompress it
+    ip_path = f'{workspace}/ip'
+    os.system( f'rm -rf {ip_path}' )
+    os.system( f'mkdir {ip_path}' )
+    os.system( f'unzip {proj_zip} -d {ip_path}' )
+
+    # Read and modify component.xml
+    component_path = f'{ip_path}/component.xml'
+    temp_path = f'{ip_path}/component.temp'
+    with open(component_path, 'r') as infile, open(temp_path, 'w') as outfile:
+        xil_family = """
+<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">zynquplusRFSOC</xilinx:family>
+<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
+"""
+        for line in infile:
+            if 'xilinx:family' in line:
+                outfile.write(xil_family)
+            else:
+                outfile.write(line)
+
+    # Replace the original component.xml with the modified one
+    shutil.move(temp_path, component_path)
+
+    # Compress the modify IP directory to the target's image directory
+    os.system( f'bash -c "cd {ip_path}; zip -r {build_zip} *"' )
+
+else:
+    # Copy the .ZIP file to the local ip/ directory
+    shutil.copy(proj_zip, build_zip)
+
+print( f'\n\n\nHLS output file: {build_zip}' )

vitis/hls/create_proj.py

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+#!/usr/bin/env python3
+##############################################################################
+## This file is part of 'SLAC Firmware Standard Library'.
+## It is subject to the license terms in the LICENSE.txt file found in the
+## top-level directory of this distribution and at:
+##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+## No part of 'SLAC Firmware Standard Library', including this file,
+## may be copied, modified, propagated, or distributed except according to
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+
+import vitis
+import os
+import shutil
+
+# Project variables
+workspace = os.getenv("OUT_DIR")
+comp_name = os.getenv("PROJECT")
+cfg_file  = f'{os.getenv("PROJ_DIR")}/hls_config.cfg'
+
+# Verify that the configuration file exists
+if not os.path.exists(cfg_file):
+    raise FileNotFoundError(f"The configuration file {cfg_file} does not exist.")
+
+# Check if component directory does not exist yet
+if not (os.path.isdir( f'{workspace}/{comp_name}' )):
+
+    # Create a client object
+    client = vitis.create_client()
+
+    # Set workspace
+    client.set_workspace(workspace)
+
+    # Create hls component with existing cfg file
+    hls_test_comp = client.create_hls_component(
+        name     = comp_name,
+        cfg_file = cfg_file,
+    )
+
+    # Print component information
+    hls_test_comp.report()
+
+    # Close the client connection and terminate the vitis server
+    vitis.dispose()