using gpuAsyncCore from AxiePcieReg

slaclab · Nov 6, 2024 · edaac02 · edaac02
1 parent 202b37f
commit edaac02
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Showing 2 changed files with 2 additions and 7 deletions.
diff --git a/firmware/python/DrpTDetGpu/_DevKcu1500.py b/firmware/python/DrpTDetGpu/_DevKcu1500.py
@@ -25,6 +25,7 @@ def __init__(self,
 
         self.add(pcie.AxiPcieCore(
             useSpi=True,
+            useGpu=True,
             offset      = 0x0000_0000,
             numDmaLanes = numDmaLanes,
             expand      = False,
@@ -58,12 +59,6 @@ def __init__(self,
             expand    = False,
         ))
 
-        self.add(pcie.AxiGpuAsyncCore(
-            name     = 'AxiGpuAsyncCore',
-            offset    = 0x00D0_0000,
-            expand    = False,
-        ))
-
         self.add(drp.I2CBus(
             name     = 'I2CBus',
             offset    = 0x00E0_0000,

diff --git a/firmware/targets/DrpTDetGpu/hdl/DrpTDetGpu.vhd b/firmware/targets/DrpTDetGpu/hdl/DrpTDetGpu.vhd
@@ -166,7 +166,7 @@ architecture top_level of DrpTDetGpu is
    constant I2C_INDEX_C     : integer := 3;
 
    constant CORE_I2C_C          : boolean                                                 := false;
-   constant NUM_AXIL0_MASTERS_C : integer                                                 := ite(CORE_I2C_C, 4, 5);
+   constant NUM_AXIL0_MASTERS_C : integer                                                 := ite(CORE_I2C_C, 3, 4);
    signal mAxil0ReadMasters     : AxiLiteReadMasterArray (NUM_AXIL0_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C);
    signal mAxil0ReadSlaves      : AxiLiteReadSlaveArray (NUM_AXIL0_MASTERS_C-1 downto 0)  := (others => AXI_LITE_READ_SLAVE_EMPTY_OK_C);
    signal mAxil0WriteMasters    : AxiLiteWriteMasterArray(NUM_AXIL0_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C);