v1.4 changelog

[gkasprow]

• changed TPS62175DQC to TPS62148RGX (oscillation on P7V5A, P7V0A #20)
• C175 10nF ->100pF (oscillation on P7V5A, P7V0A #20 )
• pulled OSK to P3V3_DVDD_IO
• added Si510 footprint DNP by default (crystal oscillator availability #18)
• added CVHD950 oscillator Vctrl input pin divider. It may be needed when VCXO oscillator is installed in case of poor availability of the standard part. (crystal oscillator availability #18)
• added mounting holes for CPCIS adapter
• replaced front panel LEDs with LED_DIALIGHT_571-0112F
• SMA connectors moved 1mm to the panel
• R87 : 1k8 -> 160R to satisfy IC18 requirement. P2V0 -> P2V1
• changed IC21 to LT3045
• added 9910 and 9912 panel design files

[hartytp]

I did a basic design review of all ICs on Urukul focussing on:

• abs max ratings
• typical application circuits
• recommended capacitors
• skim of important device parameters like drop out voltages
• pin descriptions

didn't see anything other than the reported issues. NB didn't look at overall design or info not on the schematic (capacitor voltage ratings etc)

[hartytp]

Great, thanks for doing all that! @gkasprow can you confirm that all open issues marked with a v1.4 milestone are now complete (I just did some tagging, so please re-check). If so, great!

[hartytp]

@gkasprow from a quick look, it seems that a few of these issues still aren't fixed. I'm keen to get v1.4 off to manufacture asap. Can you have a go at fixing them and then upload a new rc? Thanks!

[hartytp]

@gkasprow ping...what's the timeline for the next Urukul revision

[gkasprow]

I'm still out of the office but I'm slowly working on it.
I will be back in 4 days.

[hartytp]

That's fine, we can wait a few more days (enjoy your holiday!). Thanks for the update.

[gkasprow]

done.

[hartytp]

added CVHD950 oscillator Vctrl input pin divider. It may be needed when VCXO oscillator is installed in case of poor availability of the standard part. (#18)

Remind me why we'd ever want a VCXO and not an XO?

[hartytp]

I've reviewed the schematics. Other than #33 I don't see any issues.

Once you've fixed that and @jordens has signed off, let's send these cards to order (we have a Creotech order that's been blocked by this release for quite a while).

[gkasprow]

We don't need VCXO. It is just in case we use VCXO due to poor availability of XO

[hartytp]

Ok

[hartytp]

Oh and can you add the dds pn to the panel? Then I think we’re good to go

[hartytp]

Thanks @gkasprow!

Assuming @jordens is happy to sign off, let’s send this off to manufacture

[gkasprow]

I'm just checking with PI simulations if everything is fine.

[gkasprow]

It looks like I didn't break anything related to power delivery network.

[gkasprow]

I drafted the new release. Please have a look at the panels.

[hartytp]

ping @jordens

[jordens]

I'm ok with the changes as described and did a test-port of the CPLD gateware. But I didn't review anything else.

[hartytp]

Okay, I've reviewed everything apart from the CPLD changes. So, if you've checked that then I'm happy to cut this release here.

Thanks all!