SPI chip select set incorrectly

[jamolnng]

According to the FE310 Manual the csid register is log2(cs_width)

This implies:

For SPI 0x10024000

Binary	CS
00	CS0
01	CS1
10	CS2
11	CS3

However, in the code https://github.com/sifive/freedom-metal/blob/v201908-branch/src/drivers/sifive_spi0.c#L117 it is set like a cs_width register where each bit corresponds to each chip select line. So the register would act like this

For SPI 0x10024000

Binary	CS
0001	CS0
0010	CS1
0100	CS2
1000	CS3

A fix would be

/* Set CS line */
METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSID) = config->csid;

[nategraff-sifive]

Thanks for this too @jamolnng!