Merge pull request #222 from sifive/fix-spi-phase-pol-cs

Fix SPI polarity/phase and chip select
sifive · Mar 9, 2020 · d30ec29 · d30ec29
2 parents 1504333 + 518bfc5
commit d30ec29
Showing 1 changed file with 5 additions and 5 deletions.
diff --git a/src/drivers/sifive_spi0.c b/src/drivers/sifive_spi0.c
@@ -82,19 +82,19 @@ static int configure_spi(struct __metal_driver_sifive_spi0 *spi,
     /* Set Polarity */
     if (config->polarity) {
         METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) |=
-            (1 << METAL_SPI_SCKMODE_PHA_SHIFT);
+            (1 << METAL_SPI_SCKMODE_POL_SHIFT);
     } else {
         METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) &=
-            ~(1 << METAL_SPI_SCKMODE_PHA_SHIFT);
+            ~(1 << METAL_SPI_SCKMODE_POL_SHIFT);
     }
 
     /* Set Phase */
     if (config->phase) {
         METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) |=
-            (1 << METAL_SPI_SCKMODE_POL_SHIFT);
+            (1 << METAL_SPI_SCKMODE_PHA_SHIFT);
     } else {
         METAL_SPI_REGW(METAL_SIFIVE_SPI0_SCKMODE) &=
-            ~(1 << METAL_SPI_SCKMODE_POL_SHIFT);
+            ~(1 << METAL_SPI_SCKMODE_PHA_SHIFT);
     }
 
     /* Set Endianness */
@@ -123,7 +123,7 @@ static int configure_spi(struct __metal_driver_sifive_spi0 *spi,
     }
 
     /* Set CS line */
-    METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSID) = 1 << (config->csid);
+    METAL_SPI_REGW(METAL_SIFIVE_SPI0_CSID) = config->csid;
 
     /* Toggle off memory-mapped SPI flash mode, toggle on programmable IO mode
      * It seems that with this line uncommented, the debugger cannot have access