Merge pull request #325 from sifive/esat294-l2cc-update

Add #If defs to check if L2PM counters are available.
sifive · Aug 24, 2020 · 5546cbc · 5546cbc
2 parents fe54251 + c93a7ef
commit 5546cbc
Showing 1 changed file with 10 additions and 1 deletion.
diff --git a/src/drivers/sifive_ccache0.c b/src/drivers/sifive_ccache0.c
@@ -259,6 +259,7 @@ int sifive_ccache0_set_way_mask(uint32_t master_id, uint64_t waymask) {
 
 void sifive_ccache0_set_pmevent_selector(uint32_t counter, uint64_t mask) {
 
+#if METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS > 0
     if (counter < METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS) {
         SIFIVE_CCACHE0_ACQUIRE_LOCK
 
@@ -267,30 +268,37 @@ void sifive_ccache0_set_pmevent_selector(uint32_t counter, uint64_t mask) {
 
         SIFIVE_CCACHE0_RELEASE_LOCK
     }
+#endif
+    return;
 }
 
 uint64_t sifive_ccache0_get_pmevent_selector(uint32_t counter) {
     uint64_t val = 0;
 
+#if METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS > 0
     if (counter < METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS) {
         SIFIVE_CCACHE0_ACQUIRE_LOCK
         /* Get event selector for specified L2 event counter */
         val = REGD(METAL_SIFIVE_CCACHE0_PMEVENTSELECT0 + counter * 8);
 
         SIFIVE_CCACHE0_RELEASE_LOCK
     }
+#endif
     return val;
 }
 
 void sifive_ccache0_clr_pmevent_counter(uint32_t counter) {
 
+#if METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS > 0
     if (counter < METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS) {
         SIFIVE_CCACHE0_ACQUIRE_LOCK
         /* Clear specified L2 event counter */
         REGD(METAL_SIFIVE_CCACHE0_PMEVENTCOUNTER0 + counter * 8) = 0;
 
         SIFIVE_CCACHE0_RELEASE_LOCK
     }
+#endif
+    return;
 }
 
 uint64_t sifive_ccache0_get_pmevent_counter(uint32_t counter) {
@@ -299,6 +307,7 @@ uint64_t sifive_ccache0_get_pmevent_counter(uint32_t counter) {
 #else
     uint64_t val = 0;
 #endif
+#if METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS > 0
     if (counter < METAL_SIFIVE_CCACHE0_PERFMON_COUNTERS) {
         /* Set counter register offset */
         counter *= 8;
@@ -317,7 +326,7 @@ uint64_t sifive_ccache0_get_pmevent_counter(uint32_t counter) {
 
         SIFIVE_CCACHE0_RELEASE_LOCK
     }
-
+#endif
 #if __riscv_xlen == 32
     return ((((unsigned long long)vh) << 32) | vl);
 #else