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sicajc/README.md

Hi there 👋

Welcome! This is sicajc, a graduate student in EECS at NCHU.

Quick Bio

  • I am currently a graduate student in NCHU working on computer architecture and struggling in algorithm.

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  1. my_dc_notes Public

    Logic synthesis for Design compiler. notes

    4 2

  2. A-Single-Path-Delay-32-Point-FFT-Processor Public

    Forked from jasonlin316/A-Single-Path-Delay-32-Point-FFT-Processor

    A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

    Verilog

  3. Command Public

    2

  4. Personal-notes-for-Computer-architecture Public

    Jupyter Notebook 2

  5. VLSI_DSP_Notes_HW_Project Public

    C 4

  6. Hardware_templates_and_notes Public

    Verilog 1

209 contributions in the last year

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Contribution activity

April 2025

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