Merge PDLs into Pharo-ArchC #42
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…t a signed 32-bit integer from a read operation in its registers.
* "0d86fb5" from https://github.com/shingarov/arm.git into arm * "38c5b25" from https://github.com/shingarov/x86.git into x86 * "df8f9a9" from https://github.com/shingarov/powerpc.git into powerpc * "189b927" from https://github.com/shingarov/riscv.git into riscv * "603c175" from https://github.com/shingarov/mips.git into mips * "073b0a6" from https://github.com/shingarov/sparc.git into sparc
This commit introduces pretty much a complete rewrite of RISC-V 64 PDL
using custom extension to read instruction specifications from
`riscv-opcodes` [1]. `riscv-opcodes` are indirectly used by other
tools such as GCC / GDB.
However, this uses a new syntax - `_ac_riscv_opcodes("...");` - and
therefore this is Pharo-ArchC [2] specific.
[1]: https://github.com/riscv/riscv-opcodes.git
[2]: https://github.com/shingarov/Pharo-ArchC
...that this file uses Pharo-ArchC specific extensions.
…-A-extensions RISC-V: enable F, D and A extensions
This commit add assembly syntax for `tw` and `twi` instructions to allow assembling (and disassembling) generic traps, like tw 0, 0, 0 ; trap never or twi 31, 0, 0 ; trap always It also removes 31 from `%trapcond` map to disallow `tw 0,0` which does not make much sense (and GAS does not allow it).
See Green Cloth, §3.3.11, pp.101-105.
Using as the authoritative source: Gerry Kane. MIPS RISC Architecture (ISBN 0-13-584293-X), p.D-2.
Attempt to assemble 'syscall' was failing due to rt, rs, rd, shamd floating unbound.
This commit add PowerPC64 defined in `powerpc/powerpc64.ac` (and in included files). It reuses `powerpc/powerpc_isa.ac` to define instructions common on PowerPC and PowerPC64 (in other words, `powerpc64_isa.ac` only defines 64-bit specific instructions).
This reverts commit 45dd293 as `td` and `tdi` are now defined in `powerpc64_isa.ac`.
This commit unifies `bc`, `bca`, `bcl` and `bcla` into single
instruction. Ultimately, Power ISA, Version 3.1B as well as "green-cloth"
book as single instruction ("Branch Conditional B-form") with different
mnemonics.
Also, this will later on simplify implementation of branch mnemonics
incorporating conditions (section C.2.3 of Power ISA, Version 3.1B)
See Power ISA, Version 3.1B, Section C.2.3 Branch Mnemonics Incorporating Conditions.
Add PowerPC64 support
Green Cloth p.389.
This commit merges in PDL repository [1] to simplify development. [1]: https://github.com/janvrany/Pharo-ArchC-PDL, commit 39b1325 Merge remote-tracking branch 'pdl/master' into pr/merge-pdl
As PDLs are now part of Pharo-ArchC repository, it no longer makes sense to be able to specify directory with PDLs. This commit removes that support.
As PDLs are now part of Pharo-ArchC repository, there's no need to check out PDL. This commit updates makefiles and README accordingly. There's one issue with RISC-V PDL as it uses to upsteam `riscv-opcodes` to provide list of instructions and encodings. Technically it is an submodule so a special care is needed to make sure it is checked out. This is not a problem when one is using makefiles as they care for this, but it is a problem when relying solely on Iceberg / Metacello to load ArchC since there's no support for submodules.
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This PR merges contents of PDL repository into this one, preserving history.
Vast majority of the commits in this PR are commits from PDL repository, the new ones are: