GitHub - samuelcomeau6/verilog-modules: Useful Verilog Modules

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
Makefile		Makefile
README		README
assert.v		assert.v
seven_seg.v		seven_seg.v
seven_seg_tb.v		seven_seg_tb.v
uart.v		uart.v
uart_tb.v		uart_tb.v

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The personal verilog library of Samuel Comeau.
No use of these files without direct permission is allowed.

Useful Verilog Modules

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