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Document that isize/usize are at least 16-bit wide on all platforms we currently support #154
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TL;DR: this documents that for all practical purposes So I started guaranteeing that The current guarantee says that the layout of However, this also means that if our platform doesn't have a C platform, or a C standard conforming platform, not much about the layout of There is the "issue" of |
Note that even "8-bit" CPUs mostly have 16-bit address spaces, even though that means that a memory address cannot fit into a single register. For example, in the Intel 8008 and derivatives, addresses are specified using two 8-bit registers 'H' and 'L' (high and low), which the CPU concatenates to form a 16-bit address. |
Good point. We can drop the last commit, and make this a real guarantee. I'm not sue what the full implications of that are, or whether we are already making this guarantee, so I changed that to at least document current behavior. But if we can guarantee this without draw-backs, we should. 8-bit pointers sound like a extremely limiting concept to me. If one is restricted by that, writing code for such a target probably won't look like Rust at all. |
This doesn't belong in the unsafe code guidelines. It belongs in the core language documentation. In particular, it affects whether or not we can implement |
@briansmith feel free to open a PR to the core language documentation to document this there as well. although I'm not sure where you could put this there. Probably in the |
@briansmith note that this here is just a statement about "all platforms we support right now". It doesn't exclude the possibility of adding support for other platforms in the future; that is beyond the WG's power. |
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LGTM.
This is something that we already document, but was not explicitly spelled out.
cc @gankro